stuck-at fault

**Stuck-At Fault** is the **most fundamental fault model in digital IC testing** — modeling a defect as a signal line permanently fixed at logic 0 (Stuck-At-0, SA0) or logic 1 (Stuck-At-1, SA1), regardless of what the circuit tries to drive. **What Is a Stuck-At Fault?** - **Model**: A net is "stuck" at a constant value. - **SA0**: The line is always 0 (as if shorted to Ground). - **SA1**: The line is always 1 (as if shorted to VDD). - **Detection**: Apply a pattern that sensitizes the fault (drives the opposite value) and propagates it to an observable output. **Why It Matters** - **ATPG Foundation**: The basis for Automatic Test Pattern Generation algorithms (D-Algorithm, PODEM, FAN). - **Coverage Metric**: "Stuck-At Fault Coverage" (e.g., 98.5%) is the standard quality metric for test programs. - **Simplicity**: While real defects are more complex, stuck-at models catch ~85% of physical defects. **Stuck-At Fault** is **the ABC of chip testing** — the simplest fault model that forms the foundation of the entire test engineering discipline.