Sub Radix 2

Sub-radix-2, also called redundant SAR, is the architectural fix for exactly the capacitor-mismatch and missing-code problems DNL already quantifies — instead of sizing a CDAC's capacitors to exact binary ratios, the array deliberately uses weights slightly smaller than true binary, trading a small amount of raw conversion efficiency for something a perfectly binary-weighted array can never offer: the ability to digitally correct a wrong bit decision after the fact.

The reason an exactly binary-weighted array has zero room for error is a direct consequence of how its weights relate to each other. In a true binary array, each bit's weight equals exactly one more than the sum of every smaller bit's weight combined — an eight-weighted bit equals exactly one more than four plus two plus one. This means every bit decision in the SAR search is final and irreversible: once a bit is decided, there is no way for any later, smaller-weighted decision to compensate if that earlier decision was wrong, because the total range every remaining bit together can possibly correct is exactly one unit smaller than what a single wrong decision at that bit would cost. A capacitor mismatch, a settling error, or any other source of an incorrect bit decision in a purely binary array produces a permanent, uncorrectable error in the final result — precisely the mechanism behind the missing-code failure already covered as DNL's worst case.

Sub-radix-2 weighting breaks this zero-margin relationship by deliberately undersizing each capacitor relative to true binary, so the sum of all smaller weights now exceeds any single bit's own weight rather than falling exactly one short of it. With a radix modestly below two — common values sit around 1.8 rather than exactly 2 — the sum of every remaining smaller-weighted capacitor is now genuinely larger than the current bit's own weight, creating real overlap between what one bit decision covers and what the combination of all later bits can still reach. That overlap is the redundancy the architecture is named for: if an earlier bit decision turns out to be wrong, later bits now have enough combined range to correct for it, something the exactly-binary array could never offer no matter how the later bits were decided.

This redundancy comes at a real cost, which is a digital decoding step that a purely binary architecture never needs. Because the capacitor weights no longer correspond directly to simple binary place values, the raw sequence of bit decisions the SAR search produces cannot be read off as an ordinary binary number — it has to be digitally reconstructed by summing each decision weighted by that bit's actual, non-binary analog weight, a calculation a plain binary SAR converter's output register never has to perform. This digital correction logic adds real design complexity and a modest amount of extra silicon, but it is a trade most high-resolution SAR ADC designs accept readily, because what it buys in exchange — tolerance for real-world capacitor mismatch without requiring near-perfect binary ratios — is exactly the problem DNL and INL exist to quantify when that mismatch isn't corrected.

The benefit extends beyond capacitor matching to something equally valuable for high-speed design: relaxed settling-time requirements on every individual bit decision. In a purely binary array, each bit's comparison has to settle essentially completely before the decision is trusted, since there is no mechanism to recover from an incompletely-settled, marginally-wrong decision. With redundancy built into the weighting, a bit decision made slightly before full settling — close enough to correct, but not perfectly accurate — still falls within the range later redundant bits can correct for, which means each individual bit-decision cycle can run faster than a purely binary design would tolerate, directly raising the achievable conversion rate for a given capacitor array and comparator.

The cost of this redundancy is measured directly in extra bit cycles, typically one to four beyond the converter's nominal resolution, which is the specific number a sub-radix-2 SAR ADC's datasheet reports as its redundant bits. Each additional redundant cycle widens the error-tolerance margin further but also lengthens the overall conversion time per sample, since the SAR search now runs more comparison cycles than the converter's final resolution alone would require — a direct tradeoff between how much margin the architecture buys against mismatch and settling error, and how many extra cycles that margin costs in conversion time.

Sub-radix-2 is the architectural answer to a problem this series has already built up from two directions — the capacitor mismatch a CDAC inherits from its own binary-weighted array, and the missing-code failure DNL quantifies when that mismatch goes uncorrected — solved not by making the analog components more precise, but by giving the digital decoding logic enough redundant information to correct for imprecision that was never eliminated in the first place. It is a direct illustration of a broader principle this series keeps returning to: a hard analog precision problem is frequently cheaper to solve by adding deliberate margin and digital correction than by chasing ever-tighter component matching alone.