synthesis strategy
**Synthesis Strategy** is the **set of constraints and directives that guide logic synthesis to optimize for area, speed, or power** — determining how the synthesizer maps RTL code to a gate-level netlist using standard cells from the target library.
**Synthesis Objectives**
- **Area optimization**: Minimize gate count / chip area. Use smallest cells, share logic, reduce fanout.
- **Timing optimization**: Meet clock frequency. Use faster cells, restructure critical paths, maximize parallelism.
- **Power optimization**: Minimize switching activity. Use lower-drive cells, clock gating, multi-Vt assignments.
- **Most synthesis is timing-driven**: Area and power come second to timing closure.
**SDC (Synopsys Design Constraints) — Core Inputs**
```tcl
create_clock -name CLK -period 1.0 [get_ports CLK] # 1GHz clock
set_input_delay -clock CLK -max 0.3 [all_inputs] # Input arrival time
set_output_delay -clock CLK -max 0.2 [all_outputs] # Output required time
set_max_area 0 # Minimize area after timing met
```
**Synthesis Effort Levels**
- **Compile**: Default — balances quality vs. runtime.
- **Compile -scan**: Include scan insertion during synthesis.
- **Compile_ultra**: Maximum quality — structural optimizations, datapath restructuring. Slower.
- **Incremental Compile**: Fix specific paths without re-synthesizing entire design.
**Path Groups**
- Define priority groups: Critical path group gets highest optimization effort.
- Example: Clock_path > Reg2Reg > In2Reg > Reg2Out.
- Allocate timing budget to each path group.
**Timing-Driven Logic Restructuring**
- **Register retiming**: Move flip-flop boundary across combinational logic to balance path lengths.
- **Logic duplication**: Duplicate high-fanout cell to reduce net capacitance.
- **Constant propagation**: Propagate known constants (tied signals) through logic.
- **Resource sharing removal**: Sharing multipliers saves area but increases path depth.
**Multi-Vt Assignment**
- Start with SVT cells everywhere.
- Upsize to LVT on critical paths (timing closure).
- Downsize non-critical paths to HVT (leakage savings).
- Typical: 10–20% LVT, 60–70% SVT, 20–30% HVT for balanced design.
Synthesis strategy is **the translator between designer intent and physical gates** — the quality of synthesis determines whether the design can close timing, meet area targets, and achieve power budgets long before physical design begins.