thermal aware physical design

**Thermal-Aware Physical Design** is the **IC design methodology that considers temperature distribution during placement, routing, and floorplanning — mitigating thermal hotspots by spreading high-power-density blocks across the die, optimizing thermal conductivity paths to the heat sink, and inserting on-chip temperature monitors, because localized overheating reduces transistor performance (mobility degradation), increases leakage power exponentially, accelerates electromigration, and can cause thermal runaway in extreme cases**. **Why Thermal Matters in Physical Design** Power density in modern processors reaches 1-2 W/mm² average, with hotspots exceeding 5 W/mm² in arithmetic units. Temperature increases by 10-20°C above package capability at hotspots. Effects: - **Performance**: Carrier mobility drops ~4% per 10°C → frequency drops 3-5% per 10°C at constant voltage. Dynamic thermal management (DTM) throttles the clock when temperature limits are reached. - **Leakage Power**: Subthreshold leakage approximately doubles per 10°C increase. Thermal-leakage positive feedback: higher temperature → more leakage → more heat → higher temperature. Must be checked for thermal stability. - **Reliability**: Mean-time-to-failure for electromigration scales exponentially with temperature (Arrhenius law). A 10°C reduction in operating temperature can double interconnect lifetime. **Thermal Modeling in Physical Design** - **Compact Thermal Model**: RC network approximating the heat flow path — die → TIM (thermal interface material) → heat spreader → heat sink → ambient. Each layer modeled as thermal resistance (°C/W) and thermal capacitance (J/°C). Tools: HotSpot, ANSYS Icepak, Cadence Celsius. - **Power Map**: 2D power density distribution from post-route power analysis. Each standard cell or block has a power value from switching + leakage analysis. - **Temperature Map**: Solving the heat equation (steady-state or transient) on the power map with boundary conditions from the package thermal model. Resolution: 10-100 μm grid. **Thermal-Aware Placement Techniques** - **Power Spreading**: During placement, add a thermal penalty to the cost function — dense packing of high-power cells is penalized. This spreads hot cells across a larger area, reducing peak temperature at the cost of slightly longer wires. - **Thermal-Driven Floorplanning**: Place high-power blocks (ALU, caches, clock network) adjacent to heat-sink contact points. Interleave high-power and low-power blocks. Position I/O ring (low power) between high-power compute clusters. - **Lateral Heat Spreading**: Metal fill and power grid copper in upper metal layers conduct heat laterally toward cooler die regions. Thick redistribution layers (RDL) in advanced packaging improve lateral thermal conductivity. **On-Chip Temperature Monitoring** - **Diode Sensors**: Forward-biased PN junction voltage drops ~2 mV/°C. Simple, small, but requires calibration. 5-20 sensors distributed across the die. - **Ring Oscillator Sensors**: Frequency varies with temperature (mobility-dependent). All-digital, easily integrated. Resolution: ~1°C. Calibrated against package-level thermal diode. - **Thermal Throttling**: When sensor reports temperature above threshold (typically 100-110°C for consumer, 90-95°C for server), the power management unit reduces clock frequency or voltage. Multi-level throttling: warning → mild throttle → aggressive throttle → emergency shutdown. Thermal-Aware Physical Design is **the discipline that prevents chips from destroying themselves with their own heat** — ensuring that the power density required for modern performance levels can be dissipated reliably, extending device lifetime and maintaining performance within the thermal envelope.