Thermometer Coding

# Thermometer Coding: Build DAC Value One Unit at a Time

Thermometer coding represents an integer by the number of asserted control lines in a contiguous run. In a DAC, those lines can enable nominally equal current sources or other unit elements. Increasing the code by one extends the run by one element under a fixed, nested selection rule.

The name describes the growing column of active positions. It is a representation used inside converters, not a measurement of chip temperature. The binary input interface can remain unchanged while a decoder generates thermometer controls internally.

## 1. Read the mapping

*Selected rows of a 3-bit conversion table. Here the ones grow from left to right. Bit ordering is a convention that must agree with the decoder and layout.*

For an N-bit input, a fully unary array needs 2^N − 1 unit elements to represent codes from zero through 2^N − 1. A 3-bit input therefore has eight codes and seven controlled elements. If each ideal element supplies current I, code k gives kI. With conventional unipolar scaling I = IREF/2^N, the highest output is IREF(1 − 1/2^N).

A simple logical definition is Tj = 1 when k ≥ j, for j = 1 through 2^N − 1. For example, code 3 becomes 1110000 in the illustrated ordering. This is not one-hot coding: one-hot selects one position, while thermometer coding asserts a growing number of positions.

## 2. Examine the major-carry transition

*Conceptual selection states, not transistor-level schematics or measured waveforms. The yellow markers identify changed branches. Steering destinations and complementary switch controls are omitted.*

A binary-weighted 3-bit DAC implements code 3 with weights 2I and I. Code 4 uses the 4I branch instead. All three logical controls change even though the desired analog step is only I. If their analog effects arrive at different times, a transient output error can occur.

With fixed thermometer mapping, code 3 uses the first three unit elements and code 4 adds the fourth. One element changes selection. This avoids the same large-weight exchange at that boundary, but charge injection, clock feedthrough, timing skew and settling still matter. A one-branch selection change may also require two complementary steering switches to change state.

Thermometer coding can reduce this source of major-carry glitch; it does not guarantee a glitch-free DAC. Glitch impulse depends on implementation and operating conditions, and its worst case need not occur at digital midscale.

## 3. Separate monotonicity from linearity

For an ideal additive array with fixed nested selection, each successive step adds the next positive unit current. Unequal positive unit values can therefore preserve static monotonicity while producing unequal step sizes. Monotonicity means output does not reverse as code increases; it does not mean the transfer is perfectly linear.

Mismatch produces differential nonlinearity (DNL) through step-size variation and integral nonlinearity (INL) through accumulated deviation from the chosen reference line. Common gradients, finite source output resistance and code-dependent loading can make a simple independent-unit model inadequate. The positive-increment argument assumes the newly selected unit does not change the contributions of the previously selected units.

Good layout, biasing, output compliance and matching remain necessary. Dynamic element matching can vary physical unit assignment over time; unlike fixed nested selection, it may change multiple identities for a one-code update, so its switching behavior requires separate analysis.

## 4. Use segmentation to control array size

A fully unary 12-bit DAC would require 4095 unit elements plus selection and routing. Implementations often split the input: thermometer-code the most significant portion and implement the lower portion with binary weights.

As a concrete ideal example, split a 6-bit word into a 3-bit coarse value M and a 3-bit fine value L, so k = 8M + L. Seven coarse elements each contribute 8I, while fine branches contribute I, 2I and 4I. The result spans 0 through 63I. This reduces the number of independently controlled branches relative to a fully unary array; it does not imply an equivalent reduction in total precision-device area.

At a segment boundary, the fine section resets and a coarse element turns on. Matching between sections and timing across that boundary remain important. Choose segmentation from the required dynamic performance, area, power, layout and decoding complexity rather than from branch count alone.

## 5. Verify valid words and real transitions

Check every input code against the specified mapping, including zero, full scale and segment boundaries. For a fixed increasing input sequence, verify the expected nested set of enabled elements. An invalid word such as 1101000 contains a break in the run; it is often called a bubble. In flash ADCs, comparator outputs also form thermometer-like patterns, and their encoding may need bubble-error handling. That ADC problem is distinct from constructing a DAC decoder.

Evaluate transistor-level or measured settling and glitch for adjacent steps, large jumps and representative signal patterns. Registering decoder outputs can help coordinate updates, but clock distribution and analog switch behavior still determine actual timing. Report load, sample rate, output compliance and measurement bandwidth with dynamic results.

## References

• [Analog Devices: Current-Steering Digital-to-Analog Converters](https://wiki.analog.com/university/courses/tutorials/cmos-dac-chapter) — binary weighting, equal-element architectures and practical converter tradeoffs.
• [Analog Devices AN-1444: Second-Order Effects to Consider for Continuous Precision DAC Updates](https://www.analog.com/en/resources/app-notes/an-1444.html) — switching-delay contributions to glitch impulse and limits of major-carry worst-case assumptions.