Time-Interleaved ADC
A time-interleaved ADC takes M identical converter channels running at a modest clock rate each and fires them in a staggered round-robin so the combined output samples at M times any single channel's speed, turning a 2.5 GS/s converter design problem into four 625 MS/s ones. The trick dates back to oscilloscope front ends in the 1980s and now shows up in nearly every high-speed data-acquisition chip from Texas Instruments and Analog Devices, in SerDes receivers sampling multi-gigabit serial links, and in software-defined-radio digitizers that need gigahertz bandwidth without resorting to an exotic single-core architecture.
The entire architecture lives or dies on how well the M channels can be made to look like one channel. Each sub-ADC has its own comparator offsets, its own reference-ladder gain, and its own clock-distribution delay, and any difference between channels does not average out — it shows up as a periodic spur at multiples of the input frequency plus or minus the sample rate divided by M, visible on a spectrum analyzer as unmistakable sidebands around every tone. Production parts such as TI's ADC12DJ3200 and Analog Devices' AD9208 ship with on-chip background calibration engines that continuously estimate and null these per-channel errors, because a handful of millivolts of comparator offset mismatch or a few femtoseconds of clock skew is enough to blow a 12-bit converter's spurious-free dynamic range.
Timing skew is usually the error that caps real-world performance, because it scales with signal frequency while offset and gain errors do not. A fixed one-picosecond clock-phase error between two channels is invisible on a slow signal but produces a large sampling-instant error on a multi-gigahertz tone, which is why designers budget clock-distribution skew in femtoseconds and route the sampling clock as a matched H-tree or binary tree so every sub-ADC sees the edge at the same relative delay. Foundries building these parts in 16nm or 7nm FinFET lean on digital timing-skew estimators that correlate adjacent channels' outputs during normal operation and nudge a per-channel delay line until the correlation-derived skew estimate goes to zero, avoiding the cost and brittleness of a one-time factory trim.
Interleaving trades circuit-design difficulty for calibration-system complexity, and that trade only pays off if the calibration keeps working after the chip ships. A two-channel interleaved converter is forgiving; pushing to eight or sixteen channels for multi-tens-of-gigasample-per-second front ends, the way Analog Devices' AD9213 and Teledyne's high-speed digitizer families do, means every one of those channels must be corrected continuously against drift from temperature and aging, not just trimmed once at test. Read a time-interleaved ADC's datasheet with that in mind: the headline sample rate is a statement about the clock network and the calibration loop as much as it is about any single converter core.