Time-to-Digital Converter

A time-to-digital converter is the mixed-signal circuit that turns the gap between two electrical edges into a digital number with picosecond-scale resolution, standing in for a full flash ADC wherever the thing being measured is time itself rather than voltage. A start edge arrives, a stop edge arrives some interval later, and the TDC's job is to report that interval as a binary code accurate enough to matter — in an all-digital PLL the interval is a few hundred picoseconds of phase error, in an automotive LiDAR it is the few nanoseconds a laser pulse takes to bounce off an object a few meters away, and in automated test equipment it is the propagation-delay skew that separates a passing die from a failing one.

The coarse counter and the fine delay line split one measurement into two different jobs. A reference-clock counter handles the coarse part of the interval in whole clock periods, which is cheap but limited to the clock's own resolution — at a 1GHz reference that is only 1 nanosecond — so a second stage, the fine delay line, interpolates the leftover fraction of a clock period by pushing the start edge through a chain of matched buffers and letting a bank of flip-flops latch which taps the stop edge had already passed; the number of taps the edge crossed before getting latched is the thermometer code that encodes sub-nanosecond time directly in silicon propagation delay rather than in a clock edge.

Resolution is the whole game, and a plain delay line runs out of it fast, which is why the better TDCs use a Vernier structure instead of one straight chain. A single-chain TDC's resolution is capped at one buffer's propagation delay, typically 20-80 picoseconds in a modern CMOS process, and pushing that lower by shrinking buffers alone collides with process variation long before it helps; a Vernier TDC instead routes the start edge through a chain of slightly slower delay elements and the stop edge through a chain of slightly faster ones, so the effective resolution becomes the difference between the two delays rather than either delay alone, letting designs built in ordinary digital CMOS — no exotic analog — reach single-digit-picosecond resolution, which matters because every extra picosecond of jitter in an automotive LiDAR front end costs roughly a millimeter of range accuracy at the speed of light.

Real parts put these numbers in context. Texas Instruments' TDC7200 is a dedicated time-to-digital converter chip built for exactly this job in LiDAR and flow-meter front ends, acam/TDC-GPX-style parts push multi-channel resolution into the few-picosecond range for physics and metrology work, and inside modern SoCs the same delay-line technique shows up buried in all-digital PLLs from vendors like Intel and Qualcomm, where it replaces the analog phase-frequency-detector-plus-charge-pump loop entirely with a digital time code. The same bubble-error problem that plagues flash ADCs shows up here too — a metastable flip-flop near the 1-to-0 boundary can latch a stray 0 inside the 1s or vice versa — so every real TDC pairs its delay line with a thermometer-to-binary encoder built to tolerate a bounded number of bubbles rather than assuming a clean boundary.

Read a time-to-digital converter through a propagation-delay-as-ruler lens rather than a clock-resolution lens: once time itself is encoded in how far a pulse gets down a chain of identical gates before a second pulse catches it, resolution stops being limited by the reference clock and becomes a question of how precisely two delay chains can be matched — which is exactly the problem Vernier architectures exist to solve.