timing

**Timing Closure and Optimization Techniques** is **the process of ensuring all paths in a circuit meet timing constraints through iterative optimization — using timing analysis, path optimization, and engineering change orders (ECO) to achieve closure**. Timing closure is the critical phase of chip design ensuring all paths (combinational and sequential) meet timing requirements. Static timing analysis (STA) verifies timing without simulation. STA computes longest path delay through combinational logic and evaluates setup/hold timing at flip-flops. Timing slack = required time - arrival time. Positive slack meets requirement; negative slack violates. Critical path: longest delay through combinational logic, limiting clock frequency. Identifying critical paths guides optimization. Timing optimization involves multiple strategies. Logic optimization: simplifying combinational expressions reduces gate count and delay. Boolean minimization, logic factoring, and technology mapping optimize delay. Retiming: moving flip-flops backward/forward in logic preserving functionality but redistributing delay. Retiming distributes delay across cycle, potentially improving worst-case path. Placement optimization: relocating logic closer reduces wire delay. Wire delay is significant in modern technologies. Place and route algorithms optimize placement for timing. Routing optimization: choosing shorter paths reduces delay. Clock tree synthesis: optimizing clock distribution reduces clock skew and insertion delay. Smaller skew relaxes setup timing. Multi-level gates: adding levels of gating can reduce logical effort and delay in some cases. Careful optimization of gate sizes reduces delay. Pipelining: inserting registers increases latency but may improve throughput and timing. Breaking long combinational paths into shorter pipelined stages. Parallel computation: duplicating logic and time-multiplexing can improve timing in some cases. Area grows but timing improves. Buffering: inserting inverting buffers can restore weak signals and improve timing. Intermediate buffering on long wires reduces delay. Hold time violations: require inserting delays to meet minimum delay requirements. Negative hold slack fixed with buffers/delays on inputs or on feedback. Engineering Change Order (ECO): modifying design late in flow when major retiming is infeasible. ECO changes gate instances, connectivity, or adds buffers/cells. ECO must fit within existing layout with minimal area change. Automated ECO generation creates local changes fixing violations. Timing driven place and route: optimization during placement and routing uses timing information to guide decisions. Timing requirements propagate to router, influencing path selection. Clock frequency optimization: finding maximum frequency requires binary search or gradient search over possible frequencies. Timing analysis repeated at each frequency target. Multi-corner analysis: verifying timing across PVT (process, voltage, temperature) corners ensures robustness. Corners include: slow process/low voltage/high temperature (worst case), fast process/high voltage/low temperature (best case), and others. **Timing closure requires iterative optimization combining logic retiming, placement optimization, routing, and ECO to achieve timing requirements across all paths and operating conditions.**