timing closure signoff

**Timing Closure** is the **iterative physical design process of ensuring that every signal path in the chip meets its setup and hold timing constraints under all operating conditions (PVT corners) — the single most time-consuming and challenging activity in digital chip implementation, where the gap between first-pass timing violations and signoff-clean timing determines project schedule and often requires weeks of optimization across synthesis, placement, routing, and clock tree stages**. **Setup and Hold Fundamentals** - **Setup Time**: Data must arrive at the destination flip-flop's input at least T_setup before the clock edge. Violated when the data path is too slow relative to the clock period. Fix: reduce combinational delay (resize gates, buffer insertion, logic restructuring) or increase the clock period. - **Hold Time**: Data must remain stable for at least T_hold after the clock edge. Violated when the data path is too fast relative to the clock path. Fix: insert delay buffers in the data path. Hold violations are deadly — they cause functional failures at any frequency and cannot be fixed by slowing the clock. **Multi-Corner Multi-Mode (MCMM) Analysis** Real chips must work across process, voltage, and temperature variations: - **Worst-Case Setup**: Slow corner (SS process, low voltage, high temperature) — data paths are slowest, most likely to violate setup. - **Worst-Case Hold**: Fast corner (FF process, high voltage, low temperature) — data paths are fastest, most likely to violate hold. - **Modes**: Functional mode, test/scan mode, low-power mode — each has different active clocks and constraints. Modern signoff requires clean timing across 20-50+ corner/mode combinations simultaneously. **Timing Closure Flow** 1. **Post-Synthesis**: Initial timing with estimated wire delays. Target: <5% endpoint violations. 2. **Post-Placement**: Real cell locations, estimated routing. Placement optimization fixes most setup violations by moving cells closer together. 3. **Post-CTS**: Real clock tree delays. Clock skew can help or hurt — useful skew intentionally borrows time from slack-rich paths to help slack-poor paths. 4. **Post-Route**: Actual RC parasitics from real metal routes. The final truth. SI (signal integrity) crosstalk analysis adds pessimism that may reopen violations. 5. **Signoff**: Golden STA tool (PrimeTime, Tempus) with signoff-quality extraction (StarRC, Quantus). All corners/modes must be clean before tapeout. **Optimization Techniques** - **Gate Sizing**: Upsize critical-path gates for speed, downsize non-critical gates for area/power. - **Buffer Insertion/Removal**: Add buffers to split long nets; remove redundant buffers on non-critical paths. - **Logic Restructuring**: Re-synthesize critical cones to reduce logic depth. - **Useful Skew**: Intentionally adjust clock arrival times to redistribute slack across paths. **Timing Closure is the crucible of chip design** — the convergence point where synthesis quality, physical design skill, clock architecture, and signoff rigor determine whether the chip meets its performance targets or requires costly schedule extensions and design iterations.