timing slack
**Timing Slack** is the **margin between the required arrival time and the actual arrival time of a signal at a flip-flop input** — positive slack means timing is met, negative slack means a violation exists that must be fixed before tapeout.
**Slack Formula**
$$Slack = T_{required} - T_{actual}$$
- **$T_{required}$**: When the signal MUST arrive = clock period - setup time margin.
- **$T_{actual}$**: When the signal actually arrives = clock-to-Q delay + combinational path delay.
- **Positive slack**: Path meets timing — timing is satisfied.
- **Negative slack**: Timing violation — path is too slow.
**Key Slack Metrics**
- **WNS (Worst Negative Slack)**: Most negative slack across all endpoints. Zero or positive = no setup violations. Target: WNS ≥ 0 ns.
- **TNS (Total Negative Slack)**: Sum of all negative slacks. Measures total severity of timing problem. Target: TNS = 0 ps.
- **Critical Path**: Timing path with worst (most negative or least positive) slack — the path limiting clock frequency.
**Timing Report Components**
```
Startpoint: FF_A (rising edge clocked by CLK)
Endpoint: FF_B (rising edge clocked by CLK)
Path type: max (setup)
Data path delay: 0.843 ns
(cell: 0.512 ns, net: 0.331 ns)
Clock period: 1.000 ns
Setup time: 0.087 ns
Slack (VIOLATED): -0.041 ns
```
**Setup vs. Hold Slack**
- **Setup Slack**: Data must arrive before rising clock edge. Violated by long paths (slow logic).
- **Hold Slack**: Data must not arrive too early after previous clock edge. Violated by short paths (buffers removed).
- Fixing setup: Speed up path (resize cells, reduce fanout, restructure).
- Fixing hold: Insert buffers to slow path down.
**Timing Closure Workflow**
1. Run STA (Synopsys PrimeTime, Cadence Tempus).
2. Identify top-N negative slack paths.
3. Fix: Upsize cells, remove logic stages, reroute critical nets, reduce clock uncertainty.
4. Iterate until WNS ≥ 0, TNS = 0 at all PVT corners.
Timing slack is **the fundamental metric of chip performance and correctability** — achieving zero-WNS, zero-TNS at all required timing corners is the definition of timing closure for any digital design.