tpu architecture
**TPU architecture definition and engineering boundary.** is Google’s machine-learning ASIC organization around matrix-multiply units, vector and scalar execution, high-bandwidth memory, and inter-chip interconnect. It illustrates how a domain-specific processor and compiler can turn dense tensor algebra into a scale-out training and inference system. Exact TensorCore count, MXU shape, HBM, topology, and sparse capability differ by TPU version. Google documentation describes a TensorCore as one or more MXUs plus vector and scalar units. Earlier versions use 128 by 128 systolic MXUs, while newer v6e and TPU7x documentation describes 256 by 256 MXUs. Vector units handle activations and softmax-class work; scalar units handle control and addresses; HBM supplies tensors; ICI connects chips into slices and pods. XLA tiles and lays out graphs for these resources, so shape and compilation choices are architectural behavior rather than an external detail. A useful specification begins with workloads and service objectives rather than peak arithmetic. It records tensor shapes, sparsity, precision and accumulator behavior; model size and reuse; batch and sequence distributions; latency percentiles; required throughput; memory capacity and bandwidth; host traffic; collective communication; power, thermal and area limits; availability; security; software versions; and cost. Every published number needs its operating point, data type, workload, compiler, clock, utilization method, and whether it is measured or theoretical. Without that context, TOPS, FLOPS, bandwidth, and energy figures are not comparable.
**Architecture, execution, and data movement.** A host builds and compiles a graph, infeed or storage supplies inputs, HBM holds parameters and activations, MXUs execute tiled matrix products, vector/scalar units complete the graph, collectives use ICI within a slice, and the datacenter network joins slices when required. Modern acceleration is a hierarchy: host processors orchestrate work, a runtime and compiler lower graphs into kernels, DMA engines move tensors, local SRAM captures reuse, arithmetic arrays execute dense or sparse operations, vector and scalar units handle nonlinear and control work, and external memory holds parameters and activations that do not fit on chip. Networks, package links, and coherency connect devices. The design is balanced only when compute, storage, movement, synchronization, and software can sustain one another under the target workload. Compilation is part of the architecture. Graph capture, operator legalization, fusion, layout selection, tiling, partitioning, scheduling, precision conversion, buffer allocation, collective insertion, code generation, and runtime dispatch determine whether the hardware is occupied. Dynamic shapes, small batches, irregular sparsity, unsupported operators, and host-device boundaries create bubbles or fallback. A healthy platform exposes counters and deterministic intermediate representations so teams can explain a result instead of tuning an opaque benchmark.
**Implementation and physical realization.** Hardware and XLA co-design covers array shape, precision and FP32 accumulation, memory layout, fusion, collective topology, sparse engines, host interfaces, resiliency, power, cooling, and pod scheduling. Version-specific tuning avoids assuming one generation’s dimensions apply to another. Implementation proceeds from trace-driven models and roofline analysis through microarchitecture, RTL, verification, physical design, packaging, firmware, compiler, runtime, framework integration, and fleet qualification. Designers budget cycles and bytes for every stage, size queues against burstiness, partition clock and voltage domains, place memories close to consumers, pipeline long wires, protect CDC and reset crossings, add DFT and telemetry, and reserve margin for process, voltage, temperature, aging, and workload drift. Power intent, thermal maps, package escape, signal integrity, and memory availability are architectural inputs, not late signoff details. Specialization removes instruction overhead and unnecessary data motion, but it narrows the efficient workload envelope. Larger arrays raise peak throughput yet waste lanes on unfavorable dimensions. More SRAM improves reuse but consumes die area and leakage. Narrow precision saves bandwidth and energy but demands calibration and numerically sound accumulation. Sparse execution helps only when metadata, load balance, and software preserve useful sparsity. Chiplets improve yield and reuse while adding link energy, latency, test, thermal, and package dependencies. The correct design optimizes delivered application value rather than one isolated component.
**Verification, security, and production operation.** Measure compile time, numerical accuracy, MXU utilization, HBM traffic, collective scaling, shape padding, host input, checkpointing, failures, and end-to-end model convergence across exact TPU types. Verification combines reference-model comparison, arithmetic corner cases, protocol assertions, formal checks, constrained-random traffic, coherency and memory-order tests, CDC/RDC, power-state verification, emulation, compiler differential testing, operator and model suites, fault injection, post-layout timing and power analysis, silicon characterization, and long-running system stress. Accuracy is checked end to end after quantization and graph transformations. Performance testing reports warmup, steady state, percentiles, utilization, throttling, error bars, and reproducible software. Recovery tests cover malformed commands, link errors, memory faults, reset during work, and partial device failure. The trust boundary includes boot ROM, fuses, device firmware, management controllers, debug, DMA, shared memory, package links, compiler artifacts, model weights, and telemetry. Secure and measured boot, authenticated firmware, anti-rollback, IOMMU isolation, memory protection, zeroization, debug authorization, side-channel review, supply-chain provenance, and incident response are designed together. Multi-tenant accelerators also require scheduling and state-clearing rules that prevent one workload from observing another. Production operation needs admission control, isolation, scheduling, observability, firmware and compiler compatibility, signed updates, rollback, health checks, thermal and power management, error containment, and capacity models. Counters should attribute stalls to compute, memory, fabric, synchronization, compilation, or host overhead. Fleet telemetry closes the loop with architecture and software teams, but collection must respect tenant boundaries and data governance. Service owners define degraded modes and replacement policy before hardware faults appear.
| TPU generation class | MXU organization | Memory/system focus | Topology note | Qualification note |
|---|---|---|---|---|
| v2/v3 | Earlier 128 by 128 class | Training with HBM | Pod interconnect | Use exact version docs |
| v4 | TensorCores with multiple MXUs | Large-scale training | 3D mesh pod class | Workload and quota context |
| v5e | Cost-oriented Cloud TPU | Training and inference | Slice configurations | Price/performance workload-specific |
| v5p | Large training plus SparseCore | Scale and embeddings | High-scale ICI | Compiler and topology tuning |
| v6e / TPU7x | 256 by 256 MXU documented | Newer generation systems | Version-specific slices | Specifications continue evolving |
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**Selection, applications, and lifecycle ownership.** Use TPU when supported JAX or PyTorch workflows, XLA graphs, available slices, model shapes, and economics fit. GPUs or other accelerators may fit broader kernels, software, or deployment constraints. Large language models, vision, recommendation embeddings, scientific ML, and managed cloud training and inference use TPUs. Requirements, workloads, datasets, model and compiler versions, architecture models, RTL, IP, timing and power constraints, package and board revisions, firmware, runtime, validation evidence, calibration, test limits, errata, field telemetry, and release approvals remain linked. A hardware generation cannot be patched like an application, so interface compatibility, diagnostic reach, spare capacity, and support lifetime matter. Cross-functional ownership prevents a local optimization from moving cost or risk into memory, packaging, cooling, software, manufacturing, or customer operations. A useful specification begins with workloads and service objectives rather than peak arithmetic. It records tensor shapes, sparsity, precision and accumulator behavior; model size and reuse; batch and sequence distributions; latency percentiles; required throughput; memory capacity and bandwidth; host traffic; collective communication; power, thermal and area limits; availability; security; software versions; and cost. Every published number needs its operating point, data type, workload, compiler, clock, utilization method, and whether it is measured or theoretical. Without that context, TOPS, FLOPS, bandwidth, and energy figures are not comparable. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.