transmission

**Transmission Gate Logic Design and CMOS Switches** is **the use of complementary transistor pairs (NMOS + PMOS) to form bidirectional switches — enabling novel logic families and high-performance analog switches**. Transmission gates (TGs) are CMOS switch pairs combining NMOS and PMOS in parallel. NMOS conducts when gate is high (passes high/low, weak 0, strong 1). PMOS conducts when gate is low (inverted control). Parallel combination passes both 0 and 1 well, enabling bidirectional switching. Control signals to NMOS and PMOS are complementary (one high, one low). Transmission gate passes input to output bidirectionally when enabled. Multiplexer Design: transmission gates naturally implement multiplexers. Multiple inputs selected to single output via gated transmission gates. 2:1 mux is single TG. 4:1 mux uses 2-level TG structure. NMOS-only NMOS passes strong 1 but weak 0 (Vth drop). PMOS-only passes strong 0 but weak 1. Transmission gates compensate, passing both equally. Transmission gate logic (TGL): uses TGs as primary switches in logic design. CMOS NAND uses TGs. CMOS NOR uses TGs. Complex logic gates (AOI, OAI) use TGs. Improves speed and reduces transistor count compared to standard CMOS. Analog switch applications: transmission gates used as analog multiplexers and switches. Enable high-impedance disconnect (off-state hundreds of megaohms). Low on-resistance (tens to hundreds of ohms). Excellent for analog signal routing. Rail-to-rail switching: transmission gate passes signals from V_ss to V_dd. Precision analog applications need rail-to-rail capability. Charge injection and glitch: switching TG causes charge to inject into connected nodes. Momentary voltage glitch occurs. Critical timing applications (sample-and-hold, multiplexed analog) suffer from charge injection. Techniques: dummy TGs, careful sizing, and timing mitigation reduce glitch. Sample-and-hold circuits: TG-based sample-and-hold is fundamental analog circuit. TG switch connects input to storage capacitor. When off, capacitor retains voltage (ideally). Charge injection causes voltage error — dummy TG on opposite rail partially cancels injection. Leakage current from TG off-resistance and junction leakage discharges capacitor over time. Refresh techniques maintain accuracy. Data routing: TGs route data signals through multiplexing trees. Complex interconnect structures use TGs. Dynamic logic: TG-based dynamic logic (domino logic) combines TGs with dynamic nodes. Precharge phases set node high; evaluate phase conditionally discharges through TGs. Faster than static logic but requires careful timing. Clock distribution: dual-rail clock signals (clock, inverted clock) enable TG-based clocking. **Transmission gates provide bidirectional switching enabling novel logic families, analog multiplexing, and high-performance circuit implementations.**