triple-well cmos

**Triple-Well CMOS** is a **process architecture that adds a Deep N-Well beneath the standard P-well** — creating an electrically isolated P-well region for NMOS transistors, enabling independent body biasing and superior noise isolation between analog, digital, and memory blocks on the same die. **What Is Triple-Well?** - **Wells**: N-well (for PMOS), P-well (for NMOS), Deep N-Well (isolates selected P-wells from substrate). - **Isolated P-Well**: Can be independently biased — different from the global P-substrate potential. - **Masks**: Requires an additional mask for the Deep N-Well implant. **Why It Matters** - **Noise Isolation**: Digital switching noise in the substrate doesn't reach isolated analog NMOS devices. - **Body Biasing**: Isolated P-well enables forward/reverse body bias for individual circuit blocks. - **SRAM**: Often used to bias SRAM arrays differently from logic for optimal read/write stability. **Triple-Well CMOS** is **private rooms within the silicon** — giving each circuit block its own isolated electrical environment for independent optimization.