Under Bump Metallization

Under-bump metallization is the thin multilayer metal stack sputtered and plated onto an IC bond pad before a solder bump ever touches it, and skipping it is not an option — solder will not wet bare aluminum, and without a diffusion barrier the tin in the bump would chew straight through the pad on its first trip through a reflow oven. The sequence an OSAT runs looks like this:

Each layer in the stack has one job, and skipping any of them fails a different way. Titanium or titanium-tungsten goes down first because it is one of the few metals that bonds well to both the oxide-covered aluminum pad and the copper above it — call it the glue layer, typically 100 to 300 nanometers, thin enough that it also doubles as the first diffusion barrier. Copper comes next, first as a thin sputtered seed layer to make the pad conductive enough to electroplate, then built up 2 to 10 micrometers thick through a patterned photoresist mold that defines exactly where the bump will sit. Nickel caps the copper specifically to stop tin from the solder bump diffusing into the copper and forming runaway Cu-Sn intermetallic compounds; without that nickel barrier, Kirkendall voiding at the Cu-Sn interface can hollow out the joint over years of thermal cycling and crack it open.

The bump that lands on top of all this depends entirely on the application. Flip-chip C4 bumps for a BGA package are tin-silver solder balls 150 to 250 micrometers apart, reflowed in a furnace until surface tension pulls them into near-perfect spheres. Micro-bumps for 2.5D stacks like TSMC's CoWoS or a high-bandwidth-memory stack shrink that pitch to 40 to 55 micrometers, which is tight enough that uneven UBM thickness across a wafer becomes a yield problem all by itself — a few hundred nanometers of plating non-uniformity can be the difference between a reliable joint and an open. OSATs including Amkor, ASE Technology, and JCET run this plating and reflow sequence at volume, using sputter tools from Applied Materials and electroplating lines tuned to keep that thickness uniform across a 300mm wafer to within single-digit percent.

Thickness control is the whole game, which is why this is a packaging topic and not just a materials-science footnote. A UBM stack that plates a little thin at the wafer edge versus the center does not fail today — it fails two years into the field when thermal cycling has had time to grow a crack through the thin spot first, which is exactly the kind of latent defect burn-in and accelerated-life testing exist to catch before it reaches a customer. Read UBM as the layer that decides whether a chip's electrical design ever survives contact with a solder joint: everything upstream — the transistor, the interconnect, the pad itself — is wasted the moment a bump lifts off a bond pad that was never properly prepared to receive it.