uniformity (cvd)

CVD uniformity refers to the consistency of deposited film thickness across the wafer surface, typically expressed as a percentage variation calculated as (Max - Min) / (2 × Mean) × 100, measured at multiple points (commonly 49 or more sites on a 300 mm wafer). Advanced semiconductor manufacturing requires thickness uniformity within ±1-2% for most CVD films, with critical applications demanding ±0.5% or better. Non-uniformity in CVD films directly impacts device performance by causing variations in etch depth during pattern transfer, capacitance differences in dielectric layers, resistance variations in conductive films, and gate oxide thickness variation affecting transistor threshold voltage. Several factors determine CVD uniformity. Temperature uniformity across the wafer is paramount because deposition rate in the surface-reaction-limited regime depends exponentially on temperature — even a 1°C variation can cause measurable thickness differences. In batch LPCVD furnaces, gas depletion along the tube length creates systematic boat-position-dependent thickness gradients, managed through temperature profiling (ramping temperature along the tube to compensate for reagent depletion) and gas injection optimization. In single-wafer PECVD systems, uniformity is controlled through multi-zone showerhead gas distribution, electrode spacing, RF power distribution, and multi-zone substrate heating. Gas flow dynamics including boundary layer formation, convective transport patterns, and recirculation zones significantly affect thickness profiles. The deposition regime matters: surface-reaction-limited processes generally provide better uniformity because rate is less sensitive to local transport conditions, while mass-transport-limited processes require careful flow engineering. Plasma uniformity in PECVD is an additional variable — non-uniform plasma density creates corresponding thickness variations. Edge effects at the wafer periphery, caused by different gas flow and thermal boundary conditions, are managed through edge exclusion zones and optimized susceptor/carrier designs. Process qualification includes uniformity mapping using spectroscopic ellipsometry or four-point probe measurements at multiple wafer positions.