uvm verification

**UVM (Universal Verification Methodology)** — the industry-standard framework for building reusable, structured verification environments in SystemVerilog. **Architecture** - **Test**: Top-level scenario configuration - **Environment (env)**: Contains all verification components - **Agent**: Groups driver, monitor, and sequencer for one interface - **Driver**: Converts transactions to pin-level signals - **Monitor**: Observes pin-level signals and converts to transactions - **Sequencer**: Generates transaction sequences - **Scoreboard**: Checks expected vs actual results - **Coverage**: Tracks which scenarios have been exercised **Key Concepts** - **Transaction-Level Modeling (TLM)**: Communicate via high-level transactions, not signals - **Factory Pattern**: Create objects by type name — enables substitution without code changes - **Phases**: Build → Connect → Run → Report (standardized simulation lifecycle) - **Coverage-Driven Verification**: Random stimulus + functional coverage measures completeness **Why UVM?** - Reusable components across projects - Standardized (Accellera) — portable between simulators - Constrained random: Automatically generate diverse test scenarios **UVM** is used by virtually every chip design team — verification consumes 60-70% of total design effort.