Verification

Verification checks whether a design satisfies its stated requirements. In chip development, that includes establishing whether the implemented logic behaves as intended across relevant operating cases. The specification is the reference, so an ambiguous or incomplete requirement can undermine even a sophisticated test environment. Verification is evidence about a defined design, not a promise of perfection.

Simulation explores behavior through selected inputs and scenarios. A testbench applies stimulus, observes results, and compares them with expected behavior. Directed tests target known cases, while constrained-random approaches explore combinations under rules. Every test still needs a meaningful check; generating activity without detecting incorrect outcomes provides little confidence.

Formal methods address properties through mathematical reasoning. A proof can establish a stated property within a defined model and assumptions, while a counterexample can expose a violation. The scope matters: proving one block-level property does not establish every system requirement. Simulation and formal analysis are complementary rather than universally interchangeable methods.

Coverage measures what the verification effort has exercised or addressed. Code coverage and functional coverage answer different questions, and neither alone proves correctness. Accellera’s later UVM guide documents coverage-driven simulation methodology; it is a useful modern explanation, not evidence that UVM itself existed in the 1990s. Keep methodology history distinct from the enduring verification problem.

The Pentium FDIV incident illustrates the consequences of a narrow missed case. A defect in an arithmetic implementation can matter even when ordinary workloads appear successful. Verification planning therefore needs corner cases, independent checking, and clear treatment of assumptions. The objective is justified confidence tied to requirements and evidence, with remaining limitations stated explicitly.

Sources and further reading. [Accellera UVM user guide, 2011](https://www.accellera.org/images/downloads/standards/uvm/uvm_users_guide_1.1.pdf); [Intel historical account of the Pentium flaw](https://timeline.intel.com/1994/pentium%27s-flaw).

Read Verification as a structured body of evidence that an implementation meets explicit requirements under stated assumptions.