Vertical GAN Device Substrate

# Vertical GaN on Native GaN Substrate

Every commercial GaN power device the earlier material in this session covered — the HEMT, the 2DEG channel, dynamic on-resistance — is a lateral device grown on silicon, with current flowing sideways across the chip between source and drain sitting next to each other on the same surface. Vertical GaN devices do something structurally different: grown on an actual bulk GaN substrate rather than silicon, with current flowing straight up through the die's thickness from a drain contact on the back to a source contact on the front, the same basic architecture silicon power MOSFETs have used for decades, just rebuilt in a wide-bandgap material.

Lateral GaN-on-silicon dominates commercial products specifically because silicon substrates are cheap and large; vertical GaN on native GaN substrate exists because that same silicon substrate caps how much voltage the device can ever block. A silicon wafer is an excellent, inexpensive growth platform for the thin GaN epitaxial layer a lateral HEMT needs, which is exactly why GaN-on-silicon became the commercial mainstream for consumer chargers and data-center power supplies. But in a lateral device, breakdown voltage is set by the lateral distance between source and drain across the chip surface — pushing voltage rating higher means making the device physically larger, eating die area and cost directly. A vertical device instead blocks voltage through the thickness of the material, which can be made as thick as needed without consuming extra lateral die area, decoupling voltage rating from chip footprint in a way lateral structures fundamentally can't.

The native GaN substrate itself is both the enabling technology and the cost barrier, since growing GaN on GaN eliminates the lattice mismatch that otherwise limits defect density and crystal quality. Growing GaN epitaxially on a native GaN substrate, rather than on silicon, means the crystal lattice of the growing layer matches the substrate underneath essentially perfectly — no lattice mismatch, which is exactly the source of dislocation defects and strain that GaN-on-silicon has to manage carefully. That lattice match lets vertical GaN devices achieve lower defect density and support thicker, higher-quality epitaxial layers than growing on silicon ever could. The tradeoff is substrate cost and availability: bulk native GaN wafers are dramatically more expensive and far less mature in supply chain terms than the silicon substrates lateral GaN relies on, which is the real reason vertical GaN remains a specialized, higher-voltage niche rather than the commercial mainstream.

Vertical GaN specifically targets the high-voltage power segment where lateral GaN's area penalty becomes genuinely prohibitive, rather than competing across the board. Applications needing blocking voltages well above what consumer power adapters and data-center supplies require — grid infrastructure, industrial high-voltage conversion, some automotive and aerospace power electronics — are exactly where lateral GaN's die-area-scales-with-voltage penalty makes a lateral device impractically large, and where a vertical device's thickness-scales-with-voltage architecture pays off despite its substrate cost premium.

GaN dynamic on-resistance (611) describes a reliability mechanism specific to the lateral HEMT's buffer-layer trapping. Vertical GaN sidesteps that particular failure mode by changing the device architecture itself, trading lateral GaN's commercial maturity and low substrate cost for a fundamentally different voltage-scaling relationship — proof that "GaN power device" already spans two genuinely distinct architectures optimized for different parts of the voltage and cost spectrum, not one single structure.