via cut

**Via cut** is a lithography and etch technique used in advanced semiconductor back-end-of-line (BEOL) processing to **selectively remove unwanted vias** (vertical connections between metal layers) from a regular via array. It provides routing flexibility by starting with a dense, regular via pattern and then cutting away the connections that aren't needed. **How Via Cut Works** - **Start with Regular Array**: First, create a dense, regular grid of vias using a single exposure. Regular arrays are much easier to pattern at tight pitches than arbitrary via placements. - **Cut Exposure**: A second lithography step exposes a "cut" pattern that identifies vias to be removed. - **Selective Removal**: The cut vias are etched away, leaving only the desired via connections. **Why Via Cut Is Used** - **Patterning Difficulty**: At advanced nodes, vias are among the hardest features to pattern — they are small, isolated, and must be precisely placed. Random via placements create the worst-case lithography conditions. - **Regular Arrays Are Easier**: Dense, periodic arrays of vias lithograph much more predictably than randomly placed vias. - **Metal Cut Analogy**: Just as metal lines are first patterned as regular arrays then cut to create line-ends (metal cut), vias are patterned regularly then cut to create the desired connectivity. **Integration in Advanced BEOL** - Modern BEOL at nodes below **7nm** increasingly uses **via-cut + metal-cut** approaches as part of a self-aligned process integration flow. - **Self-Aligned Via (SAV)**: Vias are defined by the overlap of metal patterns from adjacent layers, with via cuts removing unwanted connections. - This approach improves **yield** because the self-alignment reduces sensitivity to overlay errors. **Challenges** - **Cut Placement Accuracy**: The cut pattern must precisely remove specific vias without damaging neighboring ones — requires **tight overlay** control. - **Selectivity**: The etch process must cleanly remove the cut vias without attacking the vias that should remain or the surrounding dielectric. - **Design Rules**: Chip designers must work within the constraints of the via-array + cut paradigm, which limits via placement to grid locations. Via cut is a key enabler of **regular-pattern-based BEOL** at advanced nodes — trading some design flexibility for dramatically improved patterning manufacturability and yield.