Via Stress Migration
# Via Stress Migration
Electromigration needs current flowing to push metal atoms around — no current, no electron wind, no failure. Stress migration doesn't need current at all. A copper via sitting in a powered-down chip, carrying zero amps, can still grow a void and fail open, because the driving force isn't moving electrons, it's a gradient in mechanical stress left over from how the interconnect stack was built and how it cools.
The stress comes from copper and its surrounding dielectric wanting to shrink by different amounts as the chip cools from deposition temperature. Copper interconnect is deposited hot and then cools to room temperature along with the rest of the wafer, and copper's thermal expansion coefficient is substantially larger than silicon dioxide's or any low-k dielectric surrounding it — so as the whole stack cools, the copper wants to contract more than the rigid dielectric cage around it will allow. That mismatch leaves the copper permanently under tensile stress once everything settles at room temperature, and the stress isn't uniform everywhere: it varies with line width, via geometry, and local pattern density, creating stress gradients across the interconnect stack rather than one single uniform value.
Vacancies migrate down the stress gradient the same way heat flows down a temperature gradient, and a narrow via is exactly where that flux concentrates. Copper contains a population of vacancies — missing atoms in the lattice — and those vacancies aren't static; thermally activated diffusion lets them hop from site to site, and a stress gradient biases that random hopping into a net directional flux, from lower-stress regions toward higher-stress regions, because the vacancy's own formation energy is lower where tensile stress is higher. A narrow via connecting a wide line below to a wide line above is a geometric stress concentrator — the same effect that makes any sharp constriction in a mechanically loaded structure carry higher local stress — so vacancies throughout the surrounding copper drift toward the via and accumulate there. Enough accumulated vacancies coalesce into a physical void, and if that void grows large enough to span the via's cross-section, the via goes from a working connection to an open circuit with no current ever needing to flow to cause it.
This is why stress migration specifically targets vias sitting under wide, low-current lines — exactly the structures electromigration risk analysis tends to rate as safe. Electromigration failure risk scales with current density, so a wide line carrying modest current looks electromigration-safe by any standard Blech-length or current-density check. Stress migration doesn't care about current density at all — it cares about geometry and the stress field that geometry creates, so a via underneath a wide, lightly loaded line can still be a stress-migration risk even though it would never show up on an electromigration risk list. This is a known blind spot reliability teams at companies like TSMC and Intel specifically qualify for separately: stress-migration test structures get their own thermal-storage reliability screens (long bake at elevated temperature with zero current applied) distinct from the powered electromigration stress tests, because the two failure mechanisms need entirely different test conditions to provoke.
Via redundancy and copper-grain engineering are the two main levers against it, alongside interconnect design rules that specifically flag single-via connections under wide lines. Doubling up vias at a connection (via redundancy) means a single void has to grow large enough to kill every redundant via, not just one, which dramatically improves the odds the connection survives; controlling copper grain structure and grain-boundary density during deposition changes how fast vacancies can actually diffuse through the line toward a via, since grain boundaries are a faster diffusion path than the bulk lattice; and some design rule decks flag single-via connections under unusually wide metal specifically because that geometry is the textbook stress-migration risk pattern, pushing designers toward redundant vias in exactly the layouts a pure electromigration check would have waved through.
Flicker noise and random telegraph noise come from individual trap events at an oxide interface — microscopic, local, and present the moment the device is powered. Via stress migration is a slow, chip-wide mechanical relaxation process that keeps working on the interconnect stack whether the chip is powered or sitting in a warehouse, which is exactly why it gets qualified with its own dedicated thermal-storage test rather than folded into the usual powered-stress reliability suite.