wafer level test

**Wafer-Level Testing (Probe Testing)** is the **electrical measurement process that tests every die on the wafer before dicing and packaging — using an array of probe needles or MEMS probe cards to make temporary contact with the bond pads of each die, executing functional tests, parametric measurements, and at-speed performance binning to identify Known Good Dies (KGD), screen defective dies, and provide process feedback to the fab**. **Why Test Before Packaging** Packaging a bad die wastes the packaging cost ($1-50 per unit for advanced packages, $1000+ for 2.5D/3D assemblies). By testing at the wafer level, defective dies are marked for discard before entering the expensive packaging flow. For multi-chiplet assemblies (where each package contains 4-12 dies), ensuring every die is good before assembly is essential — a single bad chiplet renders the entire $10,000+ package worthless. **Test Types** - **WAT (Wafer Acceptance Test)**: Parametric testing of dedicated test structures (transistors, resistors, capacitors) in the scribe line between dies. Measures Vth, Idsat, Ioff, contact resistance, sheet resistance, capacitance — providing process health feedback. Performed at every critical lot, typically on 5-9 sites per wafer. - **CP (Circuit Probe / Die Sort)**: Functional testing of every die. The probe card (2,000-50,000 probe tips) contacts all pads simultaneously. Tests include: - **Continuity/Leakage**: Verify all I/O pins are connected and not shorted to adjacent pins or power rails. - **IDDQ (Quiescent Current)**: Measure static power supply current. Elevated IDDQ indicates gate oxide leakage, bridging shorts, or other defects. - **Functional/Scan Test**: Execute ATPG (Automatic Test Pattern Generation) patterns through scan chains to detect stuck-at and transition faults. Coverage >98%. - **At-Speed Test**: Apply test patterns at the maximum operating frequency to detect delay defects that pass at lower speeds. - **Performance Binning**: Measure each die's maximum frequency and minimum operating voltage. Dies are sorted into speed bins (e.g., 3.0 GHz, 3.2 GHz, 3.5 GHz) for different product SKUs. **Probe Card Technology** The probe card is the most expensive consumable in test ($50K-$500K per card for advanced nodes): - **Cantilever Probes**: Tungsten needles bent at an angle, making contact by scrubbing across the pad. Suitable for peripheral pads at >50 um pitch. - **MEMS Probes**: Micro-fabricated spring-loaded probes enabling simultaneous contact with thousands of pads at pitches down to 25-40 um. Required for area-array pad layouts. - **Probe Mark and Pad Damage**: Each probe touchdown leaves a ~5 um mark on the bond pad. Excessive probing (re-tests) can damage the pad, compromising subsequent wire bond or bump adhesion. **Known Good Die (KGD)** For chiplet-based packages, wafer-level test must achieve near-100% test coverage to guarantee KGD. Additional burn-in at the wafer level (WLBI) applies elevated voltage and temperature for hours to screen early-life failures (infant mortality) before packaging. Wafer-Level Testing is **the quality gate between fabrication and packaging** — identifying every defective die before it wastes packaging resources, and sorting every good die into the correct performance tier for maximum product value.