Wafer Slip

Wafer slip is what happens when a silicon wafer gets hot enough, fast enough, while resting on only a few support points — the thermal gradient radiating out from each contact point exceeds the crystal's critical resolved shear stress, and whole planes of atoms glide past each other along the crystal's natural slip directions, leaving permanent crosshatch dislocation lines fanning out from exactly where the wafer touched its holder.

A furnace boat or susceptor only ever touches a wafer at a few small points, and that's the problem. Vertical diffusion furnaces hold wafers in slotted quartz boats, and horizontal epitaxy reactors rest them on susceptor pins — in both cases contact area is deliberately minimized so wafers don't stick or scratch, but minimal contact means each support point is a localized heat sink or heat source relative to the rest of the wafer. During a fast temperature ramp, the region right at a contact point lags or leads the surrounding silicon by tens of degrees, and that local temperature difference is exactly what drives slip.

The mechanism is identical to Dash necking's problem, running in reverse. A dislocation needs mechanical stress to move, and here that stress comes purely from thermal expansion mismatch across a few tens of degrees, not from any physical scratch or contact force — the pin itself usually never damages the wafer surface at all. Once a dislocation starts gliding along one of silicon's slip planes, it keeps propagating along that crystallographic direction until it runs out of driving stress, which is why slip shows up as long, straight crosshatch lines radiating outward from each contact point rather than as a localized blemish right at the pin.

Furnace and reactor design is built entirely around denying slip the gradient it needs. Modern vertical furnaces use boats with more support points spread more evenly, or full-ring edge supports that touch the wafer only at its outermost millimeters where active devices never sit, specifically to shrink how far any one point's thermal lag can spread before the rest of the wafer catches up. Slower, better-controlled temperature ramp rates during the push and pull stages of a furnace cycle — the moments wafers are moving into or out of the hottest zone — matter more than peak temperature itself, because ramp rate is what sets how large a gradient any support point actually sees.

Slip is invisible until someone looks for it the right way. A slipped wafer looks completely normal to the eye and often to a standard optical inspection, because the dislocation lines are a crystallographic defect, not a surface mark — infrared scattering tomography, X-ray diffraction imaging, or birefringence inspection under polarized light are what actually reveal the crosshatch pattern. Left undetected, a slipped region behaves like any other high-dislocation-density zone: elevated leakage, poor gate-oxide integrity, and devices that fail electrical test for reasons that trace straight back to a boat pin a dozen process steps earlier.

Wafer slip and COP sit on opposite ends of the same defect story: COP is a defect the crystal grows into itself before a wafer is even cut, while slip is one the fab induces afterward, every time it hands a hot wafer to a piece of hardware that can only touch it at a few points — different causes, same lesson that where silicon physically contacts anything matters as much as what happens to it chemically.