Competing Wearout Mechanisms

# Competing Wearout Mechanisms in CMOS

A chip doesn't age from a single degradation process — NBTI, hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB), and electromigration (EM) are all running simultaneously, each accumulating damage on its own clock, and the chip fails whenever the *first* one crosses its failure threshold. This reframes reliability from "will this mechanism cause failure?" to "which mechanism wins the race, and under what conditions does the ranking change?" A design qualified safely against NBTI alone can still fail in the field if a different operating profile — higher switching activity, different voltage, a hotter ambient — happens to accelerate HCI or EM past NBTI and makes one of the other mechanisms the actual limiter instead.

This is the practical reason row 6215's overview of individual wearout mechanisms isn't the whole reliability story: each mechanism has a different stress sensitivity (NBTI cares about DC bias duration and temperature; HCI cares about switching activity and drain voltage; EM cares about current density and via geometry; TDDB cares about electric field across the gate oxide), so the same chip can be NBTI-limited in one application and EM-limited in another, purely because the workload's duty cycle and switching pattern changed which stress each mechanism actually experiences.

Guardbanding against competing mechanisms requires treating each one as an independent failure clock rather than picking the single mechanism that looks worst in isolation. A reliability team runs separate accelerated-stress characterization for NBTI (elevated temperature, elevated gate bias, DC stress), HCI (elevated drain voltage with active switching), TDDB (elevated electric field across the gate oxide), and EM (elevated current density through interconnect), extracting each mechanism's own time-to-failure model as a function of its relevant stress variables. The design's actual lifetime prediction then takes the minimum across all four models at the chip's real operating conditions — not the worst-looking single mechanism, but whichever one's predicted failure time comes first at the actual mission profile, because that's the one that will fail first in the field regardless of how much margin the other three happen to have.

This is why mission-profile-based qualification has displaced single-stress qualification in advanced-node reliability flows: a chip qualified only against a worst-case NBTI stress test (long DC bias, high temperature) looks safe on paper but says nothing about how it behaves under a bursty, high-switching-activity workload where HCI dominates instead. Modern qualification combines realistic duty-cycle, voltage, and temperature profiles pulled from actual application data, runs all four degradation models against that profile simultaneously, and reports the resulting composite lifetime — which mechanism actually limits the part, and by how much margin, under the conditions it will really see.

The self-heating connection (self-heating FinFET, id 980) matters specifically because it doesn't pick one mechanism to make worse — a hotter local channel temperature accelerates NBTI, HCI, and TDDB all at once (each has its own, usually Arrhenius-like, temperature dependence), while generally leaving EM's current-density sensitivity comparatively less affected by local channel temperature. This means self-heating can shift which mechanism dominates: a design that was EM-limited at the nominal temperature assumption can become NBTI-limited or HCI-limited once the actual, hotter local fin temperature is accounted for, silently changing the chip's true limiting failure mode without anyone changing the circuit at all.

The practical takeaway for chip design is that reliability margin can't be budgeted mechanism-by-mechanism in isolation — a design that looks safely over-margined against NBTI alone might be running with almost no margin against HCI once the real workload is accounted for. Treating wearout as a competition between independent clocks, rather than a single number, is what separates reliability engineering that holds up across diverse real-world applications from reliability engineering that only holds up against the specific stress test it was characterized against.