phase-locked loop
A phase-locked loop is a feedback circuit that continuously adjusts an internal oscillator's output so its phase and frequency stay locked to a reference signal, generating a stable, synchronized clock that can also be multiplied to a different frequency than the reference.
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**Phase-locked loops exist because many circuits need a clock signal that's precisely synchronized to some reference, whether that reference comes from outside the chip or from another clock domain within it, and a free-running oscillator on its own will always drift slightly out of sync over time.** Since continuously comparing an oscillator's output against a reference signal and feeding that comparison back to correct the oscillator can keep the two locked together indefinitely, a phase-locked loop uses exactly this kind of feedback correction, measuring any phase difference between output and reference and continuously nudging the oscillator to eliminate it.
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```
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| Aspect | Free-running oscillator | Phase-locked loop |
|---|---|---|
| Synchronization to a reference | None, drifts independently | Continuously maintained |
| Frequency relative to reference | Fixed by its own design | Can be multiplied or divided |
| Response to disturbance | No correction | Feedback corrects drift |
| Common use | Standalone timing where sync isn't needed | Clock generation and frequency synthesis |
**A phase-locked loop's core building blocks are a phase detector that measures the difference between the reference and feedback signals, a loop filter that smooths that measurement into a clean control signal, and a voltage-controlled oscillator whose frequency responds to that control signal.** Because each of these three blocks handles one specific part of the correction process, comparing, smoothing, and adjusting, together they form a continuous loop where any phase difference detected gets filtered into a correction and applied to the oscillator, closing the loop and driving that difference toward zero.
**Phase-locked loops commonly include a feedback divider that lets the output run at a multiple of the reference frequency rather than being locked to exactly the same frequency, which is extremely useful since many chips need clock frequencies that don't match any convenient external reference.** Because inserting a frequency divider into the feedback path effectively tricks the phase detector into comparing a divided-down version of the output against the reference, the loop locks the output to a multiple of the reference frequency instead of an exact match, letting a single reference generate many different useful clock frequencies.
**Phase-locked loop performance is often characterized by jitter, small unwanted variations in the output signal's timing, and lock time, how long the loop takes to settle into synchronization after a disturbance, both of which matter significantly for high-speed digital and communication systems.** Because excessive jitter can directly degrade a receiving circuit's ability to correctly sample data, and slow lock time can delay a system's readiness after startup or a reference change, phase-locked loop designers carefully tune the loop's filter characteristics to balance fast, stable locking against low jitter for each specific application's needs.
Read the phase-locked loop through a dance-partner lens: much like a dance partner continuously watches and adjusts their steps to stay perfectly in sync with the lead, a phase-locked loop continuously watches and adjusts its oscillator to stay perfectly in sync with the reference signal.