what is a redistribution layer
A redistribution layer, or RDL, is a thin layer of extra wiring built on top of a finished chip that reroutes its native connection points to new, more convenient locations — letting a chip's tightly packed internal pads connect to a package or other chips in a layout that wouldn't otherwise be possible.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Chip's native connection pads", "sub": "fixed positions set by the internal circuit design", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "RDL adds a wiring layer on top", "items": [
{ "title": "Reroutes each pad to a new location", "sub": "without changing the chip's internal design", "tone": "green" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Connections now match packaging needs", "sub": "e.g. wider spacing, different layout for advanced packaging", "tone": "orange" }
]}
]
}
```
**An RDL exists because a chip's internal circuit design and its external packaging often have very different, sometimes conflicting requirements for where connections need to be.** A chip's internal design places connection pads wherever makes sense for its internal circuitry, often tightly and irregularly spaced, while the package or neighboring chips it connects to may need those connections in a completely different layout, such as evenly spaced around the edge or matched to a specific interconnect pattern — an RDL bridges that gap by adding a layer of fine wiring on top of the finished chip that reroutes each original pad to wherever it actually needs to end up.
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| Aspect | Chip's native pads | After RDL rerouting |
|---|---|---|
| Position | Set by internal circuit design | Repositioned to match packaging needs |
| Spacing | Often tight, irregular | Can be widened, evened out |
| Internal chip design | N/A | Unchanged |
| Enables | Standard packaging only | Advanced packaging, chiplet interconnects |
**RDLs have become a foundational building block of advanced packaging techniques, since many of those techniques depend on precisely controlled connection layouts an unmodified chip wouldn't provide.** Advanced packaging approaches that connect multiple chiplets together, or that use fan-out packaging to fit more connections around a chip than its edge would normally allow, generally rely on one or more RDLs to actually create the specific wiring layout those packaging techniques need — making RDL technology a quiet but essential enabler behind much of modern chip packaging innovation.
**Building an RDL requires wafer-level processing steps that resemble chip fabrication itself, even though it happens after the underlying chip is already complete.** Because an RDL is a genuine wiring layer with its own fine patterned metal traces, creating one involves lithography, metal deposition, and other wafer-level process steps similar in kind to those used to build the chip itself — this is part of why RDL and other advanced packaging capabilities are increasingly offered by the same fabs and OSATs that handle chip manufacturing and packaging together.
**Multiple RDLs can be stacked to handle increasingly complex rerouting needs, particularly in packages connecting several chiplets together.** A single RDL can only reroute connections so far, so packaging designs with especially demanding interconnect requirements, such as linking multiple chiplets with high-bandwidth connections, may use multiple stacked RDLs to progressively route signals exactly where they need to go — reflecting how packaging complexity has grown alongside the chips it needs to support.
Read the redistribution layer through a connection-relocation lens: it doesn't change anything about how a chip works internally, it simply gives its existing connections a new, more convenient set of addresses — a deceptively simple capability that underpins much of the flexibility modern chip packaging depends on.