setup and hold time
Setup and hold time are the two timing constraints that define the window around a clock edge during which a flip-flop's input data must remain stable, with setup time covering the required stability before the edge and hold time covering the required stability after it.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Flip-flop must capture data reliably at each clock edge", "sub": "input signal needs to be stable when the edge arrives", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "Setup and hold windows define the required stability", "items": [
{ "title": "Data must not change during a window before and after the edge", "sub": "violating either window risks an unreliable capture", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Reliable data capture at every clock edge", "sub": "correct value latched in, cycle after cycle", "tone": "green" }
]}
]
}
```
**Setup and hold time exist because a flip-flop doesn't capture its input data instantaneously at the exact moment of a clock edge, it needs the input to already be stable for some time before the edge and to remain stable for some time after it, in order to reliably resolve which value to latch.** Since a flip-flop's internal circuitry needs a brief window of stable input surrounding the clock edge to settle on a clean, unambiguous value, setup time defines how long before the edge the data must already be stable, while hold time defines how long after the edge the data must continue to remain stable, together defining the full stability window required for reliable capture.
```svg
```
```svg
```
| Aspect | Setup time | Hold time |
|---|---|---|
| Applies to the period | Before the clock edge | After the clock edge |
| Violation risk | Data changes too close before capture | Data changes too soon after capture |
| Typical fix | Slow the path down, ease timing | Add delay to the path |
| Common use | Bounding maximum path delay | Bounding minimum path delay |
**Setup time violations occur when data arrives too close to the clock edge, typically because the combinational logic feeding the flip-flop takes too long to produce a stable result, and they're addressed by speeding up that logic path or relaxing the clock period.** Because a setup violation means the flip-flop simply didn't have enough time to see stable data before it needed to capture, timing analysis tools flag any path whose delay leaves too little margin before the next clock edge, and designers respond by optimizing that specific path's speed or, where the whole design allows it, slowing the clock down.
**Hold time violations occur when data changes too soon after the clock edge, typically because a path is too fast rather than too slow, and they're addressed by deliberately adding delay to that path rather than trying to speed anything up.** Because a hold violation happens when new data races in and overwrites the value a flip-flop was still in the process of capturing from the previous edge, fixing it means inserting additional delay elements into that overly fast path, a notably different fix from the speed-up approach used for setup violations.
**Both setup and hold time constraints must be satisfied simultaneously across every timing path in a design, since a fix that helps one type of violation can sometimes worsen the other, making static timing analysis an essential step in verifying a design's timing correctness before manufacturing.** Because setup violations call for making paths faster while hold violations call for making paths slower, and a single change can shift a path's delay in ways that help one constraint while hurting the other, chip designers rely on comprehensive static timing analysis across the whole design to make sure every single path satisfies both setup and hold requirements together.
Read setup and hold time through a photograph lens: much like a subject needs to hold still for a brief moment both before and after the shutter clicks to avoid a blurry photo, a flip-flop's input data needs to hold still for a brief window both before and after the clock edge to avoid an unreliable capture.