static timing analysis
Static timing analysis, or STA, is a verification technique that checks whether every signal path in a chip design can meet its required timing without needing to simulate the chip's actual switching behavior, examining the design's structure mathematically instead.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Chip contains an enormous number of possible signal paths", "sub": "simulating every real switching scenario would be impractical", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "Static timing analysis mathematically checks every path", "items": [
{ "title": "Each path's delay computed and compared against requirements", "sub": "no functional simulation of actual signal switching needed", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Timing violations identified across the entire chip", "sub": "confirms the design can run reliably at its target speed", "tone": "green" }
]}
]
}
```
**Static timing analysis exists because a modern chip contains far too many possible signal paths and switching scenarios for functional simulation to exhaustively verify that every single path meets its timing requirements in a practical amount of time.** Since a signal path's delay can actually be calculated directly from the physical and electrical properties of the gates and wires it passes through, without needing to simulate the chip actually running, static timing analysis instead mathematically computes the worst-case delay along every path in the design and compares it against the timing the design requires, exhaustively checking every path's timing without the impractical computational cost of full functional simulation.
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| Aspect | Functional simulation | Static timing analysis |
|---|---|---|
| Coverage of possible paths | Limited to simulated scenarios | Exhaustive across the whole design |
| Computational cost | High for full coverage | Much lower |
| Checks actual logic correctness | Yes | No, timing only |
| Common use | Functional verification | Timing closure verification |
**Static timing analysis separately checks two distinct types of timing violations, setup violations, where a signal arrives too late, and hold violations, where a signal arrives too early, since both represent different ways a design's timing can fail.** Because a properly functioning digital circuit needs signals to arrive within a specific timing window relative to the clock, neither too late nor too soon, static timing analysis checks both setup timing, ensuring signals aren't too slow, and hold timing, ensuring signals aren't too fast relative to a nearby clock edge, since either kind of violation can cause a chip to malfunction.
**Static timing analysis accounts for manufacturing and environmental variation by analyzing timing across multiple defined corners, combinations of conditions like temperature, voltage, and manufacturing variation that represent realistic best-case and worst-case scenarios.** Because a chip's actual timing behavior varies somewhat with manufacturing differences, operating temperature, and supply voltage, static timing analysis is typically run across several such defined corners rather than just one nominal condition, ensuring the design's timing holds up correctly across the range of real-world conditions the chip will actually experience.
**Static timing analysis is central to the chip design process's timing closure step, where designers iteratively fix identified violations until every checked path in the design meets its timing requirements.** Because a design with unresolved timing violations risks malfunctioning once manufactured, chip design teams treat static timing analysis results as the primary guide for making further layout and design adjustments, repeatedly re-running the analysis and refining the design until the whole chip passes timing across all the relevant analysis corners.
Read static timing analysis through a building-inspection lens: rather than watching every possible way people might actually move through a building to see if hallways are wide enough, an inspector can instead measure every hallway directly against the required width, checking every path mathematically rather than by observing real foot traffic.