whole-chip esd protection
**Whole-chip ESD protection** is the **system-level methodology for simulating and verifying ESD current paths across an entire integrated circuit** — ensuring that every possible pin-to-pin discharge scenario has a safe, low-impedance current path and that no internal circuit element is exposed to voltage or current levels that exceed its damage threshold.
**What Is Whole-Chip ESD Protection?**
- **Definition**: A comprehensive ESD analysis approach that models the entire chip's power distribution network, I/O protection devices, and internal circuits to verify ESD robustness for all pin combinations.
- **Pin-to-Pin Analysis**: An ESD event can occur between ANY two pins — a chip with 500 I/O pins has 124,750 unique pin pairs that must all have safe discharge paths.
- **Current Path Tracing**: Simulates where ESD current actually flows, identifying "sneak paths" where current might route through weak internal logic instead of the intended ESD clamp network.
- **Voltage Verification**: Confirms that no node in the chip exceeds its voltage tolerance during any ESD scenario.
**Why Whole-Chip ESD Analysis Matters**
- **Sneak Path Detection**: Without whole-chip analysis, designers may miss current paths that route through unprotected internal circuits, causing hidden ESD failures.
- **IR Drop Verification**: Long power bus lines create voltage drops during ESD events — whole-chip simulation reveals where internal voltages exceed safe limits.
- **Cross-Domain Events**: Modern SoCs have multiple power domains — ESD events between pins in different domains create complex cross-domain current paths.
- **CDM Verification**: Charged Device Model events involve the entire die charging and then discharging through a single pin — whole-chip simulation is the only way to verify CDM robustness.
- **First Silicon Success**: ESD failures discovered after tapeout require expensive mask revisions — whole-chip verification catches these issues during design.
**Whole-Chip Analysis Flow**
**Step 1 — Netlist Extraction**:
- Extract the complete chip netlist including all ESD devices, power grid resistance, substrate resistance, and I/O pad connections.
- Include parasitic bus resistance (typically modeled as R-mesh from power grid extraction).
**Step 2 — ESD Scenario Definition**:
- Define all required zap scenarios: each pin to VDD, each pin to VSS, pin-to-pin for critical combinations.
- Apply standard ESD pulse waveforms (HBM: 100 ns decay, CDM: 1 ns rise time).
**Step 3 — Circuit Simulation**:
- Run transient SPICE simulation for each scenario using ESD-specific compact models.
- Track voltage at every sensitive node and current through every protection device.
**Step 4 — Results Analysis**:
- Flag any node where voltage exceeds its oxide breakdown threshold.
- Flag any ESD device where current exceeds its failure threshold (It2).
- Identify sneak paths where current flows through unintended routes.
**Key Tools**
| Tool | Vendor | Function |
|------|--------|----------|
| Calibre PERC | Siemens EDA | ESD connectivity and rule checking |
| PathFinder | Synopsys | Whole-chip ESD current path analysis |
| TakeCharge | Sofics | ESD simulation and optimization |
| Totem | Ansys | Power grid IR drop and ESD analysis |
| Spectre/HSPICE | Cadence/Synopsys | Circuit-level ESD transient simulation |
**Design Rules for Whole-Chip ESD**
- **Bus Width**: VDD/VSS buses must be wide enough to carry ESD current without excessive IR drop (typically 2-5 µm minimum per mA of ESD current).
- **Guard Rings**: Substrate guard rings around every I/O cell to collect substrate current and prevent latchup triggering.
- **Clamp Spacing**: Distributed clamps spaced no more than 200-500 µm apart along power buses.
- **Cross-Domain Clamps**: Dedicated ESD clamps between every pair of power domains.
Whole-chip ESD protection analysis is **the ultimate verification step for ESD robustness** — by simulating every possible discharge scenario across the entire die, designers ensure that no pin combination can create a destructive current path through unprotected circuitry.