wid (within-die variation)

WID (Within-Die Variation) Overview Within-die variation describes parameter differences across a single die, caused by systematic process gradients and random device-level fluctuations. At advanced nodes, WID variation is the dominant source of circuit performance spread. Sources of WID Variation - Systematic (Spatial): Gradual parameter gradients across the die caused by CMP dishing, etch loading, lithography lens aberrations, and deposition non-uniformity. Predictable and partially correctable. - Random (Stochastic): Statistical fluctuations at the individual device level—random dopant fluctuation (RDF), line edge roughness (LER), metal grain granularity. Unpredictable, sets fundamental limits. Key Parameters Affected - Vt (Threshold Voltage): σ(Vt) = AVT / √(W×L), where AVT is the Pelgrom coefficient. Smaller devices → larger Vt spread. - Channel Length (Leff): LER causes random Leff variation ≈ 1-2nm (3σ). Significant when nominal Lgate < 20nm. - Film Thickness: CMP-induced thickness variation across die (100-300mm scale) affects transistor and interconnect performance. Impact - SRAM Yield: 6T SRAM cells require matched transistor pairs. WID Vt variation limits minimum operating voltage (Vmin) and cell stability. - Timing: Circuit speed variation across the die causes timing guard-banding, reducing effective frequency. - Analog Matching: Current mirrors, differential pairs, and DAC/ADC elements require tight device matching. Mitigation - Statistical Design: Guard-band for 3σ or 6σ variation in timing and power. - Layout Techniques: Common-centroid layout, dummy devices, symmetric orientation for matched transistor pairs. - Process Improvement: Reduce LER (EUV lithography), improve CMP uniformity, reduce RDF (undoped channels in FinFET/GAA).