within-die variation

**Within-die variation (WID)** is the **local parameter variation among transistors inside the same die caused by layout context, local process effects, and stochastic device physics** - it impacts path balance, SRAM stability, and analog matching even when global wafer control is strong. **What Is Within-Die Variation?** - **Definition**: Intra-die spatial spread of device parameters such as Vth, Leff, mobility, and interconnect RC. - **Scale**: Micrometer to millimeter range inside one chip. - **Sources**: Layout-density effects, CMP pattern dependency, local stress, and random atomic-scale effects. - **Modeling Forms**: Systematic spatial component plus random local mismatch component. **Why Within-Die Variation Matters** - **Timing Closure Risk**: Neighboring logic paths can diverge in delay and break setup margins. - **SRAM Sensitivity**: Bit-cell mismatch raises read/write failure probability at low voltage. - **Analog Accuracy**: Current mirrors and differential pairs depend on tight local matching. - **Power Spread**: Local leakage variation creates hotspot and standby variability. - **Design Overhead**: Extra margin and guardband are needed when WID is high. **How It Is Used in Practice** - **Characterization**: Use dedicated test structures and ring oscillators across die sites. - **Statistical Signoff**: Include WID-aware Monte Carlo and spatial correlation models. - **Mitigation**: Apply layout symmetry, dummy fill, and context-aware placement rules. Within-die variation is **the local-physics limit that determines how much of a chip can safely run near performance and voltage edges** - accurate WID modeling is essential for robust advanced-node design.