Atomic Layer Etching (ALE) Selectivity is the ability of self-limiting, cyclic etch processes to remove one material at precisely controlled atomic-scale increments while leaving adjacent materials virtually untouched, enabling the angstrom-level precision required for sub-5 nm semiconductor device fabrication.

ALE Process Fundamentals:

• Two-Step Cycle: Step A modifies the top 1-3 atomic layers through surface adsorption (e.g., Cl₂ chemisorption on Si); Step B removes only the modified layer using low-energy ion bombardment (10-50 eV Ar⁺) or thermal activation
• Self-Limiting Behavior: each half-cycle saturates at the surface—excess reactant does not penetrate deeper, achieving etch per cycle (EPC) of 0.5-2.0 Å with <5% variation
• Directionality: anisotropic ALE uses directional ion bombardment for vertical profiles; isotropic ALE employs purely thermal or chemical removal for conformal etching in 3D structures
• Cycle Time: typical ALE cycle takes 10-30 seconds (vs milliseconds for continuous plasma etching), trading throughput for atomic-level precision

Selectivity Mechanisms:

• Energy Window Selectivity: different materials have distinct threshold energies for modified-layer removal—Ar⁺ ion energy tuned between thresholds of target (e.g., 15 eV for modified Si) and non-target (e.g., 40 eV for SiO₂) materials
• Chemical Selectivity: surface modification step preferentially reacts with target material—Cl₂ adsorbs on Si but not on SiN₃ₓ, achieving >50:1 selectivity
• Ligand Exchange ALE: for dielectrics, fluorination with HF followed by ligand exchange with trimethylaluminum (TMA) selectively etches Al₂O₃ over HfO₂ at >20:1 ratio
• Thermal ALE: sequential exposure to fluorinating agent (HF, XeF₂) and metal precursor (TMA, Sn(acac)₂) enables highly selective isotropic etching at 200-350°C

Material-Specific ALE Processes:

• Silicon ALE: Cl₂ adsorption + Ar⁺ sputtering at 20-40 eV achieves EPC of 1.2 Å/cycle with >100:1 selectivity over SiO₂
• SiO₂ ALE: C₄F₈ deposition + Ar⁺ bombardment at 30-50 eV enables controlled oxide removal with 15:1 selectivity over Si₃N₄
• SiN ALE: CH₃F/O₂ plasma modification + low-energy Ar⁺ removal achieves EPC of 1.5 Å/cycle for spacer recess applications
• Metal ALE: oxidation (O₂ plasma) followed by organic acid exposure (formic acid vapor) etches Cu, Co, and Ru at 0.5-1.0 Å/cycle

Critical Applications in Advanced Nodes:

• Gate Recess Control: ALE precisely recesses replacement metal gate height to within ±0.5 nm target, critical for Vt uniformity in nanosheet transistors
• Spacer Etch-Back: isotropic ALE removes inner spacer material between nanosheets with <0.3 nm damage to Si channels
• Contact Over Active Gate (COAG): ALE enables controlled dielectric recess between gate and source/drain contact without shorting
• Dummy Gate Removal: selective ALE removes sacrificial polysilicon gate with zero damage to surrounding high-k dielectric liner

Process Integration Challenges:

• Throughput: ALE processes 5-50x slower than conventional RIE—requires high-productivity multi-station chambers processing 4-8 wafers simultaneously
• Uniformity: ion energy and flux uniformity across 300 mm wafer must be <2% to maintain EPC uniformity—requires advanced plasma source designs
• Damage Budget: cumulative ion damage over 50-200 cycles must remain below threshold for substrate crystallinity degradation

Atomic layer etching selectivity is the enabling capability that allows semiconductor manufacturers to fabricate transistor features with sub-nanometer dimensional control, making it indispensable for nanosheet GAA, CFET, and future sub-1 nm node architectures where conventional etch processes lack the precision to meet device specifications.