Design-Technology Co-Optimization (DTCO) is the collaborative methodology where chip designers and process engineers jointly optimize transistor architecture, patterning rules, and circuit/layout design simultaneously — rather than sequentially — to achieve the best possible area, performance, and power (PPA) at each new technology node, because at sub-5 nm dimensions, neither process improvements alone nor design innovations alone can deliver sufficient scaling benefits.

Why DTCO Is Essential

In the era of easy scaling (1990s-2010s), the process team defined transistor characteristics and design rules; the design team optimized within those rules. The relationship was sequential. At 5 nm and below:

• Process improvements yield diminishing returns (3-5% per annum vs. historical 15%+).
• Design rules are so restrictive that layout area barely shrinks without design innovation.
• Interconnect RC delay dominates over transistor delay — process changes alone cannot fix routing congestion.

DTCO breaks the sequential barrier by co-developing process and design solutions.

DTCO in Practice

Standard Cell Height Reduction:

• Standard cell height determines logic density. Measured in metal-2 (M2) track pitches. Progression: 12T (28 nm) → 10.5T (14 nm) → 7.5T (7 nm) → 6T (5 nm) → 5T (3 nm) → 4.3T (2 nm target).
• Reducing from 6T to 5T requires: fewer fins per device (or narrower nanosheets), shared power rails (buried power rail, BPR), single-fin PMOS/NMOS, and modified cell architecture — all requiring process and design co-innovation.

Buried Power Rail (BPR):

• Move VDD/VSS power rails from the metal stack to below the transistors, in the silicon substrate. Frees M1 space for signal routing, enabling further cell height reduction.
• Process challenge: deep trench formation in the substrate, barrier metal deposition, and tungsten or copper fill. Via connection from BPR to transistor source/drain through the bottom of the device.
• Design challenge: power rail current density, electromigration at high current in narrow BPR, IR-drop analysis with new power delivery topology.

Backside Power Delivery Network (BSPDN):

• Deliver power from the back of the wafer using through-silicon vias (nano-TSVs). Completely separates power routing (backside) from signal routing (frontside). TSMC N2 and Intel 20A/18A target BSPDN.
• DTCO impact: designers gain 20-30% more signal routing resources; process engineers develop nano-TSV (100-200 nm diameter) and backside metallization capabilities.

Self-Aligned Processes:

• At sub-20 nm pitches, overlay limits prevent separate exposure of adjacent features. Self-aligned patterning (SAG, SAGC) uses one lithography step to define relationships between multiple features — eliminating overlay error between them.
• Design impact: certain layout configurations become possible (or impossible) based on self-aligned process capabilities. Design rules must encode what the process can and cannot self-align.

DTCO Metrics

The DTCO team evaluates co-optimized solutions against PPA targets:

• Area: Logic density in MTr/mm² (million transistors per mm²). Target: 2× per node.
• Performance: Frequency at iso-power. Target: 10-15% improvement per node.
• Power: Power at iso-frequency. Target: 25-30% reduction per node.

DTCO is the systems engineering approach that makes continued semiconductor scaling possible — the recognition that at atomic-scale dimensions, process and design cannot be optimized independently, and that the greatest gains come from innovations that span both domains simultaneously.