Design for Test (DFT)

Keywords: design for test dft,scan chain insertion,atpg test generation,built in self test bist,boundary scan jtag

Design for Test (DFT) is the set of design techniques that enhance chip testability by adding test structures (scan chains, BIST engines, test points) that enable efficient detection of manufacturing defects — transforming sequential logic into easily controllable and observable combinational logic during test mode, achieving 95-99% fault coverage while minimizing test time, test data volume, and area overhead to ensure that defective chips are identified before shipping to customers.

DFT Motivation:

• Manufacturing Defects: fabrication introduces random defects (particles, scratches, voids) and systematic defects (lithography hotspots, CMP issues); defect density 0.1-1.0 per cm² at mature nodes; 300mm² die has 30-300 potential defects
• Fault Models: stuck-at fault (signal stuck at 0 or 1) is the primary model; covers 80-90% of defects; transition faults (slow-to-rise, slow-to-fall) cover timing-related defects; bridging faults cover shorts between nets
• Test Coverage: percentage of faults detected by test patterns; target coverage is 95-99% for stuck-at faults; higher coverage reduces defect escape rate (defective chips passing test); each 1% coverage improvement reduces escapes by 10-100×
• Test Economics: test cost is 20-40% of total manufacturing cost; reducing test time and test data volume directly reduces cost; DFT enables efficient testing that would be impossible without test structures

Scan Chain Design:

• Scan Flip-Flop: standard flip-flop with multiplexer at input; normal mode uses functional input; test mode uses scan input from previous flip-flop; all flip-flops connected in serial chain (scan chain)
• Scan Insertion: replace all flip-flops with scan flip-flops; connect into one or more scan chains; typical design has 10-100 scan chains for parallel scan-in/scan-out; automated by DFT tools (Synopsys DFT Compiler, Cadence Genus)
• Scan Operation: shift test pattern into scan chain (scan-in); apply one clock cycle in functional mode (capture); shift response out while shifting next pattern in (scan-out); converts sequential test to combinational test
• Scan Overhead: scan flip-flops are 20-30% larger than standard flip-flops; scan routing adds 5-10% area; total DFT overhead is 10-20% area; performance impact <5% due to multiplexer delay

ATPG (Automatic Test Pattern Generation):

• Stuck-At ATPG: generates patterns to detect stuck-at-0 and stuck-at-1 faults; uses D-algorithm or FAN algorithm; typical coverage is 95-99%; undetectable faults are redundant logic or blocked by design constraints
• Transition ATPG: generates patterns to detect slow-to-rise and slow-to-fall faults; requires two-pattern test (initialization + transition); covers timing-related defects; typical coverage is 90-95%
• Bridging ATPG: generates patterns to detect shorts between nets; requires knowledge of physical layout (which nets are adjacent); covers 5-10% of defects not covered by stuck-at
• Compression: test patterns compressed to reduce test data volume; on-chip decompressor expands compressed patterns; 10-100× compression typical; reduces tester memory and test time

Built-In Self-Test (BIST):

• Logic BIST: on-chip pattern generator (LFSR) and response compactor (MISR); generates pseudo-random patterns; compacts responses into signature; no external patterns required; enables at-speed testing
• Memory BIST: dedicated test engine for memories (SRAM, DRAM); generates march patterns (read/write sequences); detects stuck-at, coupling, and retention faults; typical coverage >99%; essential for large embedded memories
• BIST Advantages: eliminates test data storage; enables at-speed testing (full-frequency test); supports field test and diagnostics; reduces dependency on external tester
• BIST Overhead: pattern generator and compactor add 2-5% area; BIST controller adds complexity; test time may be longer than ATPG (more patterns for same coverage)

Boundary Scan (JTAG):

• IEEE 1149.1 Standard: defines boundary scan architecture; adds scan cells at chip I/O pins; enables testing of board-level interconnects without physical probing
• TAP Controller: Test Access Port controller implements JTAG state machine; controlled by TCK (clock), TMS (mode select), TDI (data in), TDO (data out) pins; standard 4-5 pin interface
• Boundary Scan Cells: scan flip-flops at each I/O pin; can capture pin value or drive pin value; all boundary cells connected in scan chain; enables testing of PCB traces and connectors
• Applications: board-level interconnect test, in-system programming (ISP) of flash/FPGA, debug access to internal registers; essential for complex multi-chip systems

DFT Architecture:

• Scan Chain Partitioning: divide flip-flops into multiple scan chains; enables parallel scan-in/scan-out; reduces test time by N× for N chains; typical designs have 10-100 chains
• Scan Compression: use on-chip decompressor (XOR network) to expand compressed patterns; use compactor (XOR network) to compress responses; 10-100× reduction in test data volume and test time
• Test Points: add control points (force signal to 0 or 1) and observe points (make internal signal observable) to improve testability; breaks feedback loops and improves observability; 1-5% area overhead
• Clock Domain Handling: multiple clock domains require careful scan design; use lockstep clocking (all clocks synchronized during test) or separate scan chains per domain; asynchronous boundaries require special handling

At-Speed Testing:

• Timing Defects: some defects cause timing failures (slow transitions) rather than logical failures; detected only at full operating frequency; critical for high-performance designs
• Launch-On-Capture (LOC): launch transition using functional clock; requires two functional cycles; limited transition coverage due to functional constraints
• Launch-On-Shift (LOS): launch transition using scan shift clock; higher transition coverage; requires careful clock timing to avoid race conditions
• PLL/DLL Handling: at-speed test requires functional clock from PLL/DLL; PLL must lock during test; adds complexity to test flow; some designs use external high-speed clock

DFT Verification:

• Scan Connectivity: verify scan chains are correctly connected; use scan chain test patterns (all 0s, all 1s, walking 1s); detects scan chain breaks or miswiring
• Fault Simulation: simulate ATPG patterns on gate-level netlist with injected faults; verify coverage meets target; identify undetected faults for analysis
• Timing Verification: verify scan paths meet timing at test frequency; scan frequency typically 10-100MHz (slower than functional frequency); verify at-speed test timing
• DRC Checking: verify DFT structures meet design rules; check for scan cell placement violations, clock tree issues, or power domain violations

Advanced DFT Techniques:

• Adaptive Test: adjust test patterns based on early test results; focus on likely defect locations; reduces test time by 30-50% with same coverage
• Diagnosis: identify defect location from failing patterns; uses fault dictionary or simulation-based diagnosis; enables yield learning and process improvement
• Delay Fault Testing: detects small delay defects that cause timing failures; uses path delay patterns or transition patterns; critical for advanced nodes with increased variation
• Low-Power Test: test patterns cause higher switching activity than functional operation; can exceed power budget; use low-power ATPG or test scheduling to limit power

Advanced Node Challenges:

• Increased Defect Density: smaller features have higher defect density; requires higher test coverage; more test patterns needed for same coverage
• Timing Variation: increased process variation makes at-speed testing more challenging; must test at multiple frequencies or use adaptive testing
• 3D Integration: through-silicon vias (TSVs) and die stacking create new defect modes; requires 3D-specific DFT (pre-bond test, post-bond test, TSV test)
• FinFET Defects: FinFET has different defect characteristics than planar; fin breaks, gate wrap-around defects; requires updated fault models and ATPG

DFT Impact on Design:

• Area Overhead: scan flip-flops, compression logic, and BIST add 10-20% area; acceptable cost for ensuring quality
• Performance Impact: scan multiplexer adds delay to flip-flop; typically <5% frequency impact; critical paths may require special handling
• Power Impact: test mode has higher switching activity; can exceed functional power by 2-10×; requires power-aware test or test scheduling
• Design Effort: DFT insertion and verification adds 15-25% to design schedule; automated tools reduce effort; essential for achieving target yield and quality

Design for test is the insurance policy for chip manufacturing — by investing 10-20% area overhead in test structures, designers ensure that defective chips are caught before shipping, preventing costly field failures, product recalls, and reputation damage that would far exceed the cost of comprehensive DFT implementation.

Source: ChipFoundryServices — Search this topic — Ask CFSGPT