Capacitance–voltage measurement converts the bias-dependent charge response of a semiconductor structure into information about dielectric capacitance, flat-band voltage, mobile-carrier depletion, doping, interface traps, and slow charge. The instrument applies a DC bias plus a small AC perturbation and measures an admittance, but the extracted property depends on which charges can follow that perturbation, which equivalent circuit represents the device, and whether geometry, leakage, and series resistance are controlled.

A capacitance meter measures complex admittance, not an isolated physical capacitor. With a small sinusoidal voltage superimposed on DC bias, the instrument observes $Y(\omega)=G(\omega)+j\omega C(\omega)$ under a selected series or parallel equivalent-circuit model. The reported capacitance changes when that model is inappropriate. Cable and fixture parasitics, probe-pad capacitance, leakage conductance, contact resistance, substrate resistance, and dielectric loss must be de-embedded or included in a model validated over frequency. Open, short, and load corrections belong at the probe plane and under the same cabling configuration used for the device.

MOS capacitance follows the series combination of oxide and semiconductor charge response. For a planar capacitor with gate area $A$ and physical dielectric thickness $t_{ox}$,

in the simplest depletion description. Accumulation approaches $C_{ox}$ when majority carriers respond near the interface. Depletion widens the space-charge region and lowers total capacitance. In inversion, a high-frequency curve often remains near a minimum because minority carriers cannot follow the AC signal, while a sufficiently slow or quasi-static measurement can show their added response. Bias polarity and curve direction reverse between n-type and p-type substrates, so labels must follow the actual substrate and voltage convention.

Flat-band voltage translates voltage-axis displacement into effective charge only with a work-function model. A common idealized relation is

where $\phi_{ms}$ is the gate-to-semiconductor work-function difference and $Q_{eff}$ is an effective areal charge under the adopted sign convention. Fixed oxide charge, mobile ions, interface charge occupancy, gate depletion, dipoles, and processing history can all move a measured curve. Extracting one “oxide charge” from the shift requires a justified ideal reference, substrate doping, temperature, gate material, and quantum/electrostatic corrections.

Frequency selects which charge processes are visible. Majority carriers respond rapidly, inversion carriers may require generation or diffusion, interface states respond only when their capture and emission time constants fall within the measurement window, and slower border traps can appear as dispersion or hysteresis. No single “high frequency” is universal across Si, SiC, GaN, III–V, 2D channels, temperature, and trap energy. A frequency sweep with conductance data is more diagnostic than one C–V curve. Interface-trap density extracted by high–low, Terman, conductance, charge-pumping, or model-based methods is method- and energy-window-specific; agreement with an independent technique is stronger evidence than extra digits from one fit.

Reverse-biased junction C–V profiling differentiates a depletion-volume measurement. For a one-sided, planar abrupt junction of area $A$, depletion width is approximated by

and the local net ionized carrier concentration can be inferred from

with the sign adapted to the chosen reverse-bias convention. This is an electrical carrier profile, not a direct chemical dopant profile: incomplete activation, compensation, deep levels, freeze-out, and parallel conduction can separate the two. Graded junctions, nonplanar fields, finite layer thickness, and two-sided depletion require a more complete electrostatic model.

Numerical differentiation trades noise for depth resolution. Because the profile depends on the derivative of $1/C^2$, small capacitance noise, voltage-step error, or smoothing choice can create large false peaks. Larger voltage steps or stronger smoothing reduce noise but round abrupt features; larger AC amplitude averages charge response across a wider depletion interval. The analysis should disclose voltage grid, AC amplitude, derivative or fit algorithm, window width, boundary handling, and regularization. Area error is especially costly because the concentration expression contains $A^2$, while edge capacitance makes the effective electrical area bias-dependent for small structures.

st=>start: Define MOS stack or junction and the property to extract
structure=>operation: Verify area, perimeter, substrate, contacts, dielectric, and active geometry
fixture=>operation: Calibrate probe plane with open, short, load, leakage, and guarding checks
range=>operation: Choose safe bias range, AC amplitude, frequencies, delay, and sweep directions
raw=>operation: Acquire C and G with repeats, temperature, and prior-bias state recorded
quality=>condition: Leakage, series resistance, dispersion, and repeatability acceptable?
correct=>operation: Correct fixture and equivalent circuit or redesign device and recipe
model=>operation: Select MOS electrostatics, conductance, or junction depletion model
identify=>condition: Parameters identifiable over measured frequency and bias window?
aux=>operation: Add frequency, temperature, charge pumping, I-V, Hall, SIMS, or reference structures
unc=>operation: Propagate area, calibration, circuit, fitting, differentiation, and model uncertainty
out=>end: Report raw C-G-V data, extraction method, assumptions, and uncertainty
st->structure->fixture->range->raw->quality
quality(yes)->model->identify
quality(no)->correct->range
identify(yes)->unc->out
identify(no)->aux->raw

Ultra-thin and high-k stacks require more than classical ideal curves. Direct or trap-assisted tunneling adds conductance and can corrupt capacitance extraction; semiconductor quantum confinement and finite density of states add quantum capacitance; polysilicon gate depletion or metal-gate work function changes the electrostatics; border traps exchange charge across a continuum of time constants. Equivalent oxide thickness derived from raw accumulation capacitance can therefore differ from physical thickness. A self-consistent model may need dielectric layers, interfacial layer, quantum charge, leakage, and series resistance, with parameters constrained by ellipsometry, TEM, I–V, or known reference capacitors.

Sweep direction, rate, and history are independent experimental variables. A forward/reverse difference can reveal mobile ions or slow trapping, but its magnitude depends on endpoint voltages, dwell time, ramp rate, AC frequency, temperature, illumination, and the recovery period between sweeps. Excessively fast sweeps produce settling artifacts; long stress at endpoints can create the instability being measured. Deep depletion may appear when the bias outruns minority-carrier generation. A production recipe should specify preconditioning and use revisit measurements to distinguish reversible charging, drift, and permanent dielectric damage.

A defensible C–V result keeps observation, circuit correction, and physical inference separate. Preserve measured capacitance and conductance versus voltage, frequency, direction, temperature, and time before correction. Then document probe calibration, parasitic subtraction, series-resistance method, device area, chosen electrostatic model, derivative settings, parameter covariance, and rejection criteria. Reference capacitors and repeated nominally identical structures reveal whether a surprising feature follows the material, the geometry, or the measurement chain.

Capacitance–voltage metrology becomes trustworthy when every extracted thickness, charge, trap density, or doping profile can be traced back through electrostatics, response time, and the equivalent circuit to the measured admittance. That is the electrostatics-frequency-and-equivalent-circuit lens.