MOSFET: Mathematical Modeling

Keywords: mosfet equations,mosfet modeling,threshold voltage,drain current,NMOS PMOS,short channel effects,subthreshold,device physics equations

MOSFET: Mathematical Modeling

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Comprehensive equations, mathematical modeling, and process-parameter relationships

1. Fundamental Device Structure

1.1 MOSFET Components

A MOSFET is a four-terminal semiconductor device consisting of:

• Source (S) : Heavily doped region where carriers originate
• Drain (D) : Heavily doped region where carriers are collected
• Gate (G) : Control electrode separated from channel by dielectric
• Body/Substrate (B) : Semiconductor bulk (p-type for NMOS, n-type for PMOS)

1.2 Operating Principle

The gate voltage modulates channel conductivity through field effect:

1.3 Device Types

2. Core MOSFET Equations

2.1 Threshold Voltage

The threshold voltage $V_{th}$ determines device turn-on and is highly process-dependent:

Component Equations

• Flat-band voltage :

• Fermi potential :

• Oxide capacitance per unit area :

• Work function difference :

Parameter Definitions

2.2 Drain Current Equations

2.2.1 Linear (Triode) Region

Condition : $V_{DS} < V_{GS} - V_{th}$ (channel not pinched off)

Simplified form (for small $V_{DS}$):

Channel resistance :

2.2.2 Saturation Region

Condition : $V_{DS} \geq V_{GS} - V_{th}$ (channel pinched off)

Without channel-length modulation ($\lambda = 0$):

Saturation voltage :

2.2.3 Channel-Length Modulation

The parameter $\lambda$ captures output resistance degradation:

Output resistance :

Where $V_A$ is the Early voltage (typically $5$ to $50$ V/μm × L).

2.3 Subthreshold Conduction

2.3.1 Weak Inversion Current

Condition : $V_{GS} < V_{th}$ (exponential behavior)

Characteristic current :

Thermal voltage :

2.3.2 Subthreshold Swing

The subthreshold swing $S$ quantifies turn-off sharpness:

Numerical values :

• Ideal minimum: $S_{min} = 60$ mV/decade (at 300K, $n = 1$)
• Typical range: $S = 70$ to $100$ mV/decade
• $n = 1 + \frac{C_{dep}}{C_{ox}}$ (subthreshold ideality factor)

2.3.3 Depletion Capacitance

2.4 Body Effect

When source-to-body voltage $V_{SB} eq 0$:

Body effect coefficient :

Typical values : $\gamma = 0.3$ to $1.0$ V$^{1/2}$

2.5 Transconductance and Output Conductance

2.5.1 Transconductance

Saturation region :

Alternative form :

2.5.2 Output Conductance

2.5.3 Intrinsic Gain

3. Short-Channel Effects

3.1 Velocity Saturation

At high lateral electric fields ($E > E_{crit} \approx 10^4$ V/cm):

Saturation velocity :

3.1.1 Modified Saturation Current

Note: Linear (not quadratic) dependence on gate overdrive.

3.1.2 Critical Length

Velocity saturation dominates when:

3.2 Drain-Induced Barrier Lowering (DIBL)

The drain field reduces the source-side barrier:

DIBL coefficient :

Typical values : $\eta = 20$ to $100$ mV/V for short channels

3.2.1 Modified Threshold Equation

3.3 Mobility Degradation

3.3.1 Vertical Field Effect

Alternative form (surface roughness scattering):

3.3.2 Universal Mobility Model

Where $E_{eff}$ is the effective vertical field:

3.4 Hot Carrier Effects

3.4.1 Impact Ionization Current

Multiplication factor :

3.4.2 Ionization Rate

3.5 Gate Leakage

3.5.1 Direct Tunneling Current

Where:

3.5.2 Gate Oxide Field

4. Parameters

4.1 Gate Oxide Engineering

4.1.1 Oxide Capacitance

4.1.2 Equivalent Oxide Thickness (EOT)

4.1.3 Capacitance Equivalent Thickness (CET)

Including quantum effects and poly depletion:

Where:

• $\Delta t_{QM} \approx 0.3$ to $0.5$ nm (quantum mechanical)
• $\Delta t_{poly} \approx 0.3$ to $0.5$ nm (polysilicon depletion)

4.2 Channel Doping

4.2.1 Doping Profile Impact

4.2.2 Depletion Width

4.2.3 Junction Capacitance

Where:

• $C_{j0}$ = zero-bias capacitance
• $\phi_{bi}$ = built-in potential
• $m = 0.5$ (abrupt junction), $m = 0.33$ (graded junction)

4.3 Gate Material Engineering

4.3.1 Work Function Values

4.3.2 Flat-Band Voltage Engineering

For symmetric CMOS threshold voltages:

4.4 Channel Length Scaling

4.4.1 Characteristic Length

For good short-channel control: $L > 5\lambda$ to $10\lambda$

4.4.2 Scale Length (FinFET/GAA)

4.5 Strain Engineering

4.5.1 Mobility Enhancement

Where:

• $\Pi$ = piezoresistive coefficient
• $\sigma$ = applied stress

Enhancement factors :

• NMOS (tensile): $+30\%$ to $+70\%$ mobility gain
• PMOS (compressive): $+50\%$ to $+100\%$ mobility gain

4.5.2 Stress Impact on Threshold

Where $\alpha_{th} \approx 1$ to $5$ mV/GPa

5. Advanced Compact Models

5.1 BSIM4 Model

5.1.1 Unified Current Equation

5.1.2 Effective Overdrive

5.1.3 Effective Saturation Voltage

5.2 Surface Potential Model (PSP)

5.2.1 Implicit Surface Potential Equation

5.2.2 Charge-Based Current

Where $Q_i$ is the inversion charge density:

5.3 FinFET Equations

5.3.1 Effective Width

For multiple fins:

5.3.2 Multi-Gate Scale Length

Double-gate :

Gate-all-around (GAA) :

Where $r$ = nanowire radius

5.3.3 FinFET Threshold Voltage

6. Process-Equation Coupling

6.1 Parameter Sensitivity Analysis

6.2 Variability Equations

6.2.1 Random Dopant Fluctuation (RDF)

Where $A_{VT}$ is the Pelgrom coefficient (typically $1$ to $5$ mV·μm).

6.2.2 Line Edge Roughness (LER)

6.2.3 Oxide Thickness Variation

6.3 Equations:

6.3.1 Drive Current

Where $\alpha = 2$ (long channel) or $\alpha \rightarrow 1$ (velocity saturated).

6.3.2 Leakage Current

6.3.3 CV/I Delay Metric

Constants:

Equations:

Threshold Voltage

Linear Region Current

Saturation Current

Subthreshold Current

Transconductance

Body Effect

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