Artificial Intelligence University

Module 2.1: The Artificial Neuron (The Perceptron)

Biological brains contain billions of cells called neurons that pass electrical signals across microscopic gaps called synapses. In 1958, Frank Rosenblatt modeled this in mathematics as the Perceptron.

An artificial neuron takes several input numbers ($x_1, x_2$), multiplies each input by a configurable dial called a weight ($w_1, w_2$), and adds a tuning knob called a bias ($b$):

Imagine deciding whether to play soccer outside. $x_1$ represents how sunny it is ($1$ to $5$), and $x_2$ represents how much homework you have left ($1$ to $5$). If $w_1 = 0.8$ and $w_2 = -1.5$, homework has a negative weight that pulls down your decision score $z$ twice as strongly as sunshine pulls it up!

Module 2.2: The On/Off Switch — Activation Functions

If every neuron only multiplied and added numbers, stacking 100 layers of neurons would still be mathematically identical to just one single linear line: $y = mx + b$. It could never learn complex curved shapes or facial features!

To give neural networks the power to learn any curved pattern in the universe, we pass $z$ through a non-linear activation function $f(z)$:

• ReLU (Rectified Linear Unit): $f(z) = \max(0, z)$. If $z$ is negative, output 0; if positive, let $z$ pass straight through! ReLU is world-famous because it is lightning fast to compute in hardware silicon (just a simple comparator check against zero!).
• Sigmoid: $\sigma(z) = \frac{1}{1 + e^{-z}}$. Squashes any input number between $-\infty$ and $+\infty$ into a clean probability percentage between $0.0$ and $1.0$.

Module 2.3: Matrix Multiplication — The Heartbeat of AI Silicon

Real AI models do not have just one neuron; they connect thousands of inputs to thousands of outputs. In linear algebra, we group all inputs into a vector $\mathbf{x}$ and all the weights into a rectangular grid called a matrix $\mathbf{W}$:

Every single number in the output layer is computed by multiplying pairs of numbers and adding them together. Computer engineers call this a Multiply-Accumulate (MAC) operation. If a neural network has 1,024 input features and 2,048 neurons in the next layer, computing that single layer requires:

$$1,024 \times 2,048 = 2,097,152 \text{ MAC operations (approx. 4.19 MegaFLOPs)}$$

Modern AI chips are custom-designed from the silicon floorplan up to perform billions of these exact MAC operations every single microsecond!

Module 3.1: Measuring Error — The Loss Function

To train a network, we need an objective mathematical function that quantifies exactly how bad our current model's predictions are:

• Mean Squared Error (MSE): Used for continuous regression predictions (e.g. temperature, latency): $$\mathcal{L}_{\text{MSE}} = \frac{1}{2N} \sum_{i=1}^{N} \left(y_i - \hat{y}_i\right)^2$$
• Cross-Entropy Loss: Used for discrete classification (e.g. dog vs cat, token prediction in LLMs): $$\mathcal{L}_{\text{CE}} = -\sum_{k} y_k \log\left(\hat{y}_k\right)$$

The loss defines a high-dimensional surface called the loss landscape. Finding the best weights corresponds to finding the lowest valley on this mountain range.

Module 3.2: Gradient Descent & The Calculus Chain Rule

How do we find the lowest valley? We compute the gradient $\nabla \mathcal{L}$, which is the vector of partial derivatives pointing in the direction of steepest uphill ascent. We then step in the exact opposite direction:

Here, $\eta$ is the learning rate. If $\eta$ is too small, training takes weeks. If $\eta$ is too large, the optimizer overshoots the valley and explodes into numerical instability!

To compute $\frac{\partial \mathcal{L}}{\partial \mathbf{W}}$ through hundreds of hidden layers, we use the Calculus Chain Rule in reverse (Backpropagation):

$$\frac{\partial \mathcal{L}}{\partial w} = \frac{\partial \mathcal{L}}{\partial \hat{y}} \cdot \frac{\partial \hat{y}}{\partial z} \cdot \frac{\partial z}{\partial w}$$

Module 3.3: Hardware Acceleration — 2D Systolic Arrays

In a standard von Neumann CPU or GPU vector pipeline, computing a matrix multiplication requires fetching numbers from SRAM/DRAM registers into ALUs, performing one math operation, and writing the result back to registers. Memory access burns over 95% of total chip power!

To solve this, H.T. Kung and Google (with the TPU) revived the Systolic Array. In a 2D systolic array:

• Processing Elements (PEs) are arranged in a 2D grid ($N \times N$).
• Weights are pre-loaded and held stationary inside the PEs (Weight Stationary).
• Input values stream from left to right, while partial sums flow from top to bottom in a synchronized rhythmic pulse (like blood pumping through a heart!).
• Intermediate data is handed directly to the neighboring PE without writing back to the register file, slashing memory bandwidth and energy by up to 10x!

Module 4.1: Convolutions vs Sequence Modeling

For decades, neural architectures divided by data domain:

• Convolutional Neural Networks (CNNs): Convolve small learnable spatial filter kernels (e.g. $3 \times 3$) across 2D/3D tensor grids. Key properties: weight sharing and translation equivariance. Highly efficient for spatial patterns, but intrinsically localized.
• Recurrent Neural Networks (RNNs/LSTMs): Process sequential data token-by-token, maintaining a hidden state vector $\mathbf{h}_t = \tanh(\mathbf{W}_{hh} \mathbf{h}_{t-1} + \mathbf{W}_{xh} \mathbf{x}_t)$. Fatal hardware drawback: sequential dependency prevented GPU parallelization across time steps ($O(N)$ sequential latency), and long sequences suffered from vanishing gradients.

Module 4.2: Scaled Dot-Product Attention & The Transformer

In 2017, Vaswani et al. introduced the Transformer ("Attention Is All You Need"), replacing recurrence entirely with parallel Self-Attention. An input sequence $\mathbf{X} \in \mathbb{R}^{N \times d}$ is projected into Queries $\mathbf{Q}$, Keys $\mathbf{K}$, and Values $\mathbf{V}$:

Why divide by $\sqrt{d_k}$? When the projection dimension $d_k$ is large, dot products $\mathbf{q} \cdot \mathbf{k}$ grow proportionally large in magnitude ($\text{Var}(\mathbf{q} \cdot \mathbf{k}) \approx d_k$). Large values push the softmax function into regions of near-zero gradients (saturation), freezing backpropagation updates.

The $O(N^2)$ Memory Wall: Multiplying $\mathbf{Q} \in \mathbb{R}^{N \times d_k}$ by $\mathbf{K}^T \in \mathbb{R}^{d_k \times N}$ materializes an intermediate $N \times N$ attention matrix. At a sequence length of $N = 32,768$, storing this matrix per attention head requires billions of elements, exhausting on-chip SRAM!

Module 4.3: Numerical Formats in Silicon: FP32, FP16, BF16, FP8

Standard scientific computing relies on IEEE 754 32-bit Floating Point (FP32). However, deep learning is resilient to lower precision, allowing chips to achieve massive speedups by packing smaller data words into memory and ALUs:

• FP32 (1 sign, 8 exponent, 23 mantissa): Golden precision; standard for optimizer accumulation, but too memory-hungry for parameter storage.
• FP16 (1 sign, 5 exponent, 10 mantissa): Halves memory, but narrow 5-bit exponent (dynamic range $\sim 10^{\pm 4.5}$) causes underflow (vanishing gradients) or overflow (NaNs) during training without dynamic loss scaling.
• Bfloat16 (Brain Floating Point, 1 sign, 8 exponent, 7 mantissa): Google-designed format with the exact same dynamic range as FP32, allowing direct drop-in replacement for training without numerical divergence.
• FP8 (E4M3 and E5M2): Standardized in NVIDIA Hopper & Blackwell. E4M3 (1-4-3) provides higher precision for weights and activations, while E5M2 (1-5-2) provides wider dynamic range for backward gradients. Doubles throughput over 16-bit!

Module 5.1: Tensor Core Microarchitecture & WMMA Execution

Traditional GPU CUDA cores execute SIMT (Single Instruction, Multiple Threads) where each thread performs one scalar FMA (Fused Multiply-Add) instruction per cycle. In contrast, Tensor Cores execute warp-synchronous matrix operations:

All 32 threads in a warp cooperate to load a $16 \times 16$ tile into internal register space and compute 1,024 MAC operations in a handful of clock cycles. In mixed-precision execution, inputs $\mathbf{A}$ and $\mathbf{B}$ are stored in BF16 or FP8, while accumulator $\mathbf{C}$ and result $\mathbf{D}$ are maintained in 32-bit FP32 to prevent catastrophic cancellation over thousands of additions.

Module 5.2: Modern LLM Architecture: RoPE, RMSNorm, SwiGLU, GQA

State-of-the-art foundation models (Llama 3, Mistral, Gemma) replace classic Transformer building blocks with specialized hardware-friendly primitives:

• Rotary Position Embedding (RoPE): Injects positional information by multiplying query and key vectors by a 2D rotation matrix: $$\mathbf{R}_{\Theta, m}^d = \text{diag}\left(\mathbf{R}_{\theta_1, m}, \mathbf{R}_{\theta_2, m}, \dots\right)$$ Preserves relative distances between tokens ($q_m^T k_n = g(x_m, x_n, m - n)$) and naturally generalizes to longer context lengths.
• RMSNorm (Root Mean Square Normalization): Strips out the mean-centering step of LayerNorm, saving two full passes over activations in on-chip memory: $$\bar{a}_i = \frac{a_i}{\text{RMS}(\mathbf{a})} g_i, \quad \text{RMS}(\mathbf{a}) = \sqrt{\frac{1}{d} \sum_{i=1}^{d} a_i^2 + \epsilon}$$
• SwiGLU Activation: Swish Gated Linear Unit ($\text{SwiGLU}(x) = (\text{Swish}(x W) \otimes x V) W_2$) replaces GeLU, providing superior gradient flow at the cost of one extra projection matrix.
• Grouped-Query Attention (GQA): While Multi-Head Attention maintains 1 Key-Value head per Query head ($H_Q = H_{KV}$), GQA allows multiple Query heads (e.g. 8) to share a single Key-Value head ($H_Q = 8 \times H_{KV}$). This reduces the inference KV-Cache size and memory bandwidth pressure by 8x!

Module 5.3: Williams' Roofline Model for AI Silicon

The performance of any AI hardware accelerator is governed by the Roofline Model:

Operational Intensity (OI): The ratio of floating-point arithmetic operations to DRAM/HBM memory traffic transferred:

$$OI = \frac{\text{FLOPs}}{\text{Bytes Transferred}}$$

If a workload has low $OI$ (less than the chip's ridge point $OI_{\text{ridge}} = P_{\text{peak}} / \text{BW}$), it is Memory-Bound: arithmetic ALUs sit idle over 90% of the time waiting for weights to arrive from HBM! This is why autoregressive token generation (decoding one token at a time) is strictly memory-bandwidth bound.

Module 6.1: Non-Linear Quantization & The Activation Outlier Wall

Quantizing model weights from 16-bit to 4-bit (INT4/FP4) reduces memory bandwidth and footprint by $4\times$. In uniform affine quantization, real numbers $x \in [\alpha, \beta]$ are mapped to integers:

The Emergence of Activation Outliers: Once LLMs scale past 6.7B parameters, systematic feature dimensions emerge where activation magnitudes spike to over 100x the standard channel variance (Dettmers et al., 2022). Naive INT8/INT4 quantization rounds normal channels to zero, causing catastrophic perplexity collapse!

Modern algorithmic breakthroughs solve this:

• SmoothQuant: Applies an exact per-channel diagonal scaling transformation: $\mathbf{Y} = (\mathbf{X} \text{diag}(\mathbf{s})^{-1}) \cdot (\text{diag}(\mathbf{s}) \mathbf{W})$, mathematically migrating the dynamic range difficulty from activations to weights.
• AWQ (Activation-Aware Weight Quantization): Protects the top 1% salient weight channels corresponding to large activation magnitudes, quantizing only the non-critical 99%.
• GPTQ: Employs second-order Taylor expansion and inverts the Hessian matrix $\mathbf{H}^{-1} = (2 \mathbf{X}\mathbf{X}^T)^{-1}$ to iteratively adjust remaining unquantized weights in optimal Cholesky order.

Module 6.2: 2:4 Fine-Grained Structured Hardware Sparsity

Unstructured pruning removes weights randomly based on magnitude. While mathematically attractive ($>70\%$ zeroes), unstructured sparse matrices require irregular pointer indirection and non-coalesced memory reads, resulting in zero speedup on real GPUs.

NVIDIA solved this in Ampere and Hopper through 2:4 Structured Sparsity:

• In every contiguous vector of 4 consecutive weights, exactly 2 must be zero ($50\%$ sparsity).
• The remaining 2 non-zero weights are packed into a dense half-sized vector, accompanied by a compact 2-bit index metadata per pair.
• Dedicated Sparse Tensor Cores bypass the zeroes in hardware, reading $2\times$ less data and performing matrix multiplications at $2\times$ peak theoretical throughput with negligible accuracy degradation when retrained with Straight-Through Estimators (STE)!

Module 6.3: FlashAttention: IO-Aware Tiling & Online Softmax

Standard Multi-Head Attention computes $\mathbf{S} = \mathbf{Q}\mathbf{K}^T \in \mathbb{R}^{N \times N}$, writes $\mathbf{S}$ to slow GPU High-Bandwidth Memory (HBM), reads it back to compute $\mathbf{P} = \text{softmax}(\mathbf{S})$, writes $\mathbf{P}$ to HBM, and reads it back to compute $\mathbf{O} = \mathbf{P}\mathbf{V}$. This generates $O(N^2)$ memory reads and writes!

Tri Dao's FlashAttention (2022/2023) eliminates the $O(N^2)$ HBM memory traffic through hardware-aware tiling:

FlashAttention loads blocks of $\mathbf{Q}, \mathbf{K}, \mathbf{V}$ into ultra-fast on-chip SRAM ($228\,\text{KB}$ per SM in Hopper), computes softmax incrementally without ever writing the $N \times N$ matrix to HBM, and accumulates the final output $\mathbf{O}$ on-the-fly. This slashes memory IO from $O(N^2)$ down to $O(N)$, unlocking $3\times\text{--}8\times$ wall-clock speedups!

Module 7.1: Neural Scaling Laws & Compute-Optimal Frontiers

In 2020, Kaplan et al. proposed empirical scaling laws relating model parameters $N$, dataset tokens $D$, and total training compute $C$ (in FLOPs):

In 2022, Hoffmann et al. (Chinchilla) demonstrated that previous models were severely undertrained: for compute-optimal training, model parameters and training tokens should scale in equal proportion:

$$N \propto C^{0.50}, \quad D \propto C^{0.50} \implies D \approx 20 \times N$$

The Inference-Optimal Paradigm: In commercial production where a foundation model is queried by millions of users daily, the cost of inference eclipses training cost. Therefore, modern frontier models are intentionally "overtrained" far past Chinchilla optimality (e.g. Llama 3 8B trained on 15 Trillion tokens: $D / N \approx 1,875$) to compress maximum intelligence into smaller, cheaper silicon serving footprints!

Module 7.2: 3D Parallelism Topology & Communication Collective

Training a 405B-parameter model requires terabytes of GPU memory (weights, gradients, optimizer states, activations). No single accelerator can hold the model. System architects partition the model using 3D Parallelism:

• Tensor Parallelism (TP, Megatron-LM): Splits weight matrices across GPUs within the same server node. Requires low-latency all-reduce over high-speed NVLink ($900\text{--}1,800\,\text{GB/s}$).
• Pipeline Parallelism (PP): Partitions consecutive layers across server chassis. Uses 1F1B (One Forward, One Backward) scheduling with $m$ micro-batches across $p$ stages. Theoretical bubble fraction: $$F_{\text{bubble}} = \frac{p - 1}{m + p - 1}$$
• Data Parallelism & ZeRO (Zero Redundancy Optimizer): Partitions optimizer states (ZeRO-1), gradients (ZeRO-2), and parameters (ZeRO-3) across the data-parallel world, recovering memory with minimal All-Gather overhead.
• Expert Parallelism (EP): Routes tokens to specialized Sparse Mixture-of-Experts (MoE) layers via All-to-All communication networks.

Module 7.3: Cluster Economics, MFU & Megawatt Datacenters

The efficiency of a hyperscale cluster is evaluated by Model FLOPs Utilization (MFU):

Achieving $\text{MFU} > 45\text{--}50\%$ across 16,384+ GPUs requires eliminating stragglers, scheduling deterministic collective communication, overlapping communication with compute (NCCL CUDA streams), and handling mean-time-between-failures (MTBF) of mere hours through non-blocking asynchronous NVMe checkpointing.

A 24,000 GPU cluster draws 30 to 40 Megawatts of continuous electrical power. Optimizing training schedules and minimizing cluster idle bubbles directly saves tens of millions of dollars in power and capital expenditure!