Master Semiconductor Devices
From Elementary School to PhD & Fab

1. The P-N Junction Diode

When you join P-type silicon (rich in mobile positive "holes") and N-type silicon (rich in mobile negative electrons), carriers diffuse across the boundary. They recombine and leave behind fixed ionized donor and acceptor charges, creating an insulating Depletion Region.

This creates an internal electric field and a built-in barrier potential ($V_{bi} \approx 0.7\text{ V}$ for Silicon):

• Forward Bias ($V > 0.7\text{ V}$): The external battery pushes against the built-in barrier, shrinking the depletion width and allowing a flood of current!
• Reverse Bias ($V < 0\text{ V}$): The battery widens the depletion zone, blocking current flow except for a microscopic leakage current ($I_s \approx 10^{-12}\text{ A}$).

2. From 2 Terminals to 3: The Birth of the Transistor

A diode is great for directing current one way, but it cannot amplify a signal or be controlled remotely. To build a computer, we need a three-terminal device:

• Source: The reservoir where electric charge carriers enter.
• Drain: The terminal where carriers exit the device.
• Gate: The control knob. By applying a voltage to the Gate, we open or close the bridge between Source and Drain!

1. The MOS Structure & Inversion Layer

The core of modern digital electronics is the MOSFET. In an NMOS transistor, two heavily doped $n^+$ pockets (Source and Drain) are embedded in a $p$-type silicon substrate, separated by a channel of length $L$ and width $W$.

Above the channel sits a thin dielectric insulator ($SiO_2$ or $HfO_2$) capped by a conductive gate. As we increase Gate voltage $V_{GS}$:

• Accumulation ($V_{GS} < 0$): Holes gather at the dielectric interface.
• Depletion ($0 < V_{GS} < V_{th}$): Mobile holes are pushed away, leaving negative ionized acceptors.
• Strong Inversion ($V_{GS} \ge V_{th}$): Electrons are drawn to the surface, creating an $n$-type conductive channel connecting Source to Drain!

2. Governing Current Equations: Linear vs Saturation

Once inverted, applying Drain-Source voltage $V_{DS}$ produces current $I_D$ governed by the classic quadratic model:

In saturation, the channel pinches off at the drain side, causing current to saturate at a constant plateau controlled exclusively by the gate overdrive $(V_{GS} - V_{th})$.

1. The Subthreshold Conduction Regime

When $V_{GS} < V_{th}$, a transistor is not truly OFF. Instead of drift, transport is governed by diffusion of carriers overcoming the source-to-channel energy barrier. The drain current drops exponentially with gate voltage:

where the ideality factor $m = 1 + \frac{C_d}{C_{ox}} > 1$ represents the capacitive voltage divider between gate oxide and depletion capacitance.

2. Subthreshold Swing ($SS$) & The Boltzmann Tyranny

The Subthreshold Swing ($SS$) is the gate voltage swing required to change the drain current by one order of magnitude ($10\times$):

At room temperature ($T = 300\text{ K}$), the thermal voltage is $k_B T/q \approx 25.85\text{ mV}$, which imposes an immutable fundamental physical limit:

3. Drain-Induced Barrier Lowering (DIBL)

As channel length $L$ shrinks below $100\text{ nm}$, the drain electric field penetrates deep into the channel, pulling down the source-channel potential barrier and lowering the effective threshold voltage:

1. The Collapse of Planar MOSFETs at 20nm

Below $20\text{ nm}$, planar MOSFETs suffered catastrophic short-channel effects because the gate was on only one side of the channel. Drain electric field lines penetrated through the deep substrate, bypassing the gate.

The solution was to elevate the channel into a thin, 3D vertical silicon "fin" wrapped on three sides by the gate electrode: the FinFET (Tri-Gate Transistor).

2. FinFET Effective Width ($W_{eff}$) Quantization

Because the gate wraps the top and two sidewalls of the fin, the effective conduction width per fin is strictly quantized:

Circuit designers can no longer arbitrarily widen a transistor to increase drive current. Current can only be scaled in discrete integer steps ($1\text{ fin}, 2\text{ fins}, 3\text{ fins}$).

3. Gate-All-Around (GAA) Nanosheet Architecture (3nm & 2nm)

At $3\text{ nm}$, even FinFET sidewalls leak. The industry transitioned to Gate-All-Around (GAA) Nanosheets, where horizontally stacked nanosheets are suspended, allowing the gate dielectric and metal to wrap completely around all 4 sides of each sheet:

1. Monolithic Complementary FET (CFET)

Even with GAA nanosheets, standard cell area scaling is blocked by the horizontal separation distance between nFET and pFET. The Complementary FET (CFET) solves this by folding the pFET directly beneath (or on top of) the nFET in 3D space:

CFET requires sequential or monolithic 3D epitaxy, high aspect-ratio middle-of-line (MOL) contacting, and Backside Power Delivery Networks (BSPDN) to power both top and bottom devices.

2. Breaking the Boltzmann Tyranny: Steep-Slope Switches

Conventional thermal injection is bounded by $SS \ge 60\text{ mV/dec}$. Two breakthrough device mechanisms break this boundary:

• Negative Capacitance FET (NC-FET): Incorporates a ferroelectric dielectric layer ($Hf_{x}Zr_{1-x}O_2$) undergoing Landau-Khalatnikov polarization switching. The effective negative capacitance provides internal voltage amplification ($A_v = \partial V_s / \partial V_g > 1$), yielding $SS < 60\text{ mV/dec}$!
• Band-to-Band Tunnel FET (TFET): Uses quantum mechanical tunneling across a reverse-biased p-i-n heterojunction to inject only cold electrons, filtering out the high-energy thermal tail: $$I_{BTBT} \propto \exp\left( -\frac{4\sqrt{2 m^*} E_g^{3/2}}{3 q \hbar \mathcal{E}} \right)$$

3. 2D Transition Metal Dichalcogenide (TMD) Channels

When silicon nanosheets are thinned below $3\text{ nm}$, surface roughness scattering degrades carrier mobility. Monolayer 2D crystals like $MoS_2$ and $WS_2$ have atomically pristine van der Waals surfaces with zero dangling bonds and an electrostatic screening length $\lambda < 1\text{ nm}$, enabling gate lengths down to $1\text{ nm}$.

1. Device Degradation Mechanisms

Commercial foundries qualify silicon transistors for a 10-year operating life ($100{,}000\text{ hours}$) across industrial temperature ranges ($-40^\circ\text{C}$ to $+125^\circ\text{C}$). Over lifetime, three primary degradation physics dominate:

• Negative Bias Temperature Instability (NBTI): In pFETs under high negative gate bias and elevated temperature, Si-H bonds at the dielectric interface dissociate. Trapped positive charges cause threshold voltage shift: $$\Delta V_{th}(t) = A \cdot \exp\left( \frac{\mathcal{E}_{ox}}{\mathcal{E}_0} \right) \cdot \exp\left( -\frac{E_a}{k_B T} \right) \cdot t^n \quad (n \approx 0.16 - 0.25)$$
• Hot-Carrier Injection (HCI): High lateral drain electric fields accelerate channel electrons into "hot carriers" that generate electron-hole pairs via impact ionization, damaging gate dielectrics near the drain pin.
• Time-Dependent Dielectric Breakdown (TDDB): Continuous electric field stress forms conductive percolation pathways across the gate insulator until hard dielectric breakdown occurs.

2. Process-Voltage-Temperature (PVT) Sign-off Corners

Foundry PDKs characterize statistical device variability using 5 classic process corners:

Slow-Slow (SS) at low $V_{DD}$ and high temperature sets minimum frequency ($f_{MAX}$ setup timing), while Fast-Fast (FF) at high $V_{DD}$ and sub-zero temperature governs race conditions (hold time violations) and peak thermal dissipation.

3. BSIM-CMG Compact Modeling

Modern commercial SPICE simulations utilize the BSIM-CMG (Compact Model Coalition) surface-potential-based model, capturing multi-gate quantum mechanical volume inversion, parasitics, and stress effects with high numerical convergence.