10nm-Process
A 10 nm process name identifies a supplier’s technology generation rather than a universal ten-nanometer feature. Different manufacturers reached their named platforms on different schedules and with different density targets. Device architecture, metal pitches, libraries, and manufacturing qualification all contribute to the actual capability. The number alone cannot establish equivalence.
TSMC’s 2016 report records transfer of its 10 nm process to operations in the fourth quarter. The same report describes a fast production ramp scheduled for the second half of 2017. Transfer, planned ramp, and customer product shipment are separate milestones. Keeping those stages distinct avoids turning a period forecast into evidence of an achieved event.
FinFET scaling required coordinated changes to devices and local wiring. Reducing pitch can improve potential density while increasing resistance, capacitance, and patterning difficulty. Contacts and cell pin access occupy a larger fraction of a compact layout. A process has to deliver a usable library and interconnect system as well as small transistors.
Multiple patterning adds a manufacturing and design coordination problem. Dense layouts can require decomposition into repeated exposure, etch, or spacer operations. Overlay error, pattern variability, and additional process steps affect the final result. Layout restrictions and physical verification help keep a design within the qualified patterning window.
The history also includes Intel’s separately named 10 nm development and delays. Those events belong to Intel’s platform and cannot be inferred from TSMC’s production chronology. A comparison needs dated supplier records and a consistent metric. The 10 nm generation makes the distinction between node naming, technical ambition, and manufacturable product delivery particularly visible.
Sources and further reading. [TSMC 2016 business overview](https://investor.tsmc.com/sites/ir/annual-report/2016/2016_Business_Overview_E.pdf).
Read 10 nm process as a set of distinct manufacturing programs whose density ambitions depended on difficult device, wiring, and patterning integration.