28nm-Fd-Soi

A 28 nm FD-SOI platform uses a thin silicon device layer above a buried insulating oxide. The channel body is designed to be fully depleted in its intended operating regime. The geometry provides a planar alternative to fin-based transistors at nearby named generations. The 28 nm label alone does not specify body thickness, buried-oxide thickness, or electrical limits.

The thin body and buried oxide change electrostatics and substrate coupling. Removing a neutral body region helps control the channel with reduced dependence on heavy channel doping. The insulating layer separates the device from the underlying substrate. Contacts, source/drain resistance, capacitance, and interface quality still influence the complete transistor.

Back bias provides an additional operating control when supported by the platform. A voltage applied beneath the buried oxide can shift threshold behavior through capacitive coupling. This allows trade-offs between speed and leakage within qualified bias limits. It is a separate control path from the front gate and must be modeled with its own voltage and reliability conditions.

STMicroelectronics and CEA-Leti documented UTBB FD-SOI development in this period. The 2012 CEA research report and ST’s 28 nm technical material describe the thin-body, thin-buried-oxide approach and body-bias capabilities. They establish named development and platform references. Later roadmap targets should be distinguished from the qualified 28 nm offering itself.

The platform’s value depends on the circuit and product requirements. Libraries, SRAM, analog behavior, bias-generation circuitry, and operating modes determine the realized energy benefit. Back-bias flexibility does not remove the cost of generating and distributing that bias. A useful evaluation considers the complete design across active and idle conditions.

Sources and further reading. [ST 28 nm FD-SOI technology material](https://www.st.com/content/ccc/resource/sales_and_marketing/presentation/technology_presentation/group0/35/54/24/df/5d/39/4f/39/BRFDSOI0616/files/BRFDSOI0616.pdf/jcr%3Acontent/translations/en.BRFDSOI0616.pdf); [CEA-Leti 2012 research report](https://www.cea.fr/cea-tech/leti/Documents/Rapport%20scientifique/Rapports%202012/Annual%20Research%20report%20DCOSDTSI%202012.pdf).

Read 28 nm FD-SOI as a planar thin-body CMOS platform that combines strong electrostatics with qualified back-bias control.