3D NAND Back End Bit Line Etch

Back-end bit-line etch is where the array's tightest pitch actually gets cut, and ordinary single-exposure lithography can't resolve it directly — which is why this step usually isn't a simple pattern-and-etch at all, but a self-aligned double patterning (SADP) sequence that doubles the density a single mask could otherwise achieve.

Bit-line contacts landed
BLC etch already complete
Mandrel pattern
wider features, easily resolved
Conformal spacer deposit
coats mandrel sidewalls
Mandrel removal
spacers alone remain
BL trench etch (SADP)
two trenches per mandrel, half pitch
BL metal fill
each trench lands on its own BLC

SADP works by printing something wider and easier first, then using deposition and etch together to split it into two narrower features.

Back-End Bit-Line Etch — Doubling Pitch With SADP lithography alone can't resolve this pitch, so the etch doubles what one exposure can print 1. Mandrels patterned 2. Conformal spacer deposited 3. Mandrel removed, spacers etch the BL trenches — half the original pitch BL metal fill — each trench lands on its own BLC/channel plug below The tightest pitch in the array, cut by self-aligned double patterning a single lithography exposure can't resolve bit-line pitch directly — SADP uses a wider, easily printed mandrel and a spacer etch to generate two trenches for every one mandrel, doubling the effective density. each resulting trench must still align to the BLC/channel plug underneath it, from the channel-hole module several steps earlier

Mandrels are patterned first, at a pitch lithography can actually hit reliably. These sacrificial features are deliberately wider and more loosely spaced than the final bit-line pitch requires, because the goal is never to print the bit lines directly — it's to establish a regular, well-controlled starting structure.

A conformal spacer film coats every mandrel sidewall evenly, the same deposition principle used in slit-spacer etch elsewhere in this flow, except here the spacer itself is about to become the permanent pattern rather than a disposable liner.

Removing the mandrel is what reveals the real pitch. Once the sacrificial mandrel is etched away, the spacers that were coating its two sides are left standing on their own — two features where there had been one mandrel, at exactly half the original spacing, with no lithography exposure fine enough to have printed that spacing directly.

The bit-line trench etch itself follows the pattern those surviving spacers define, cutting the actual metal trenches into the back-end dielectric at the density SADP produced rather than the density the original mask pattern alone could resolve.

Every one of those trenches still has to land on the right target several modules back in the flow. Each bit-line trench this etch cuts has to align to its own bit-line contact and channel plug — structures the BLC module and the channel-hole module finished long before SADP ever ran — so a density-doubling trick at the back end still depends on precision set much earlier in the process.

Back-end bit-line etch is proof that not every hard problem in 3D NAND is about aspect ratio or depth: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all reach a pitch here that no single lithography pass can print, and SADP's mandrel-spacer-removal sequence is simply how the industry gets a usable bit-line pattern out of a mask that, on its own, isn't fine enough.

Take 3d nand back end bit line etch further

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