3D NAND Bit Line Contact Etch

Bit-line contact etch looks like the simplest contact in the whole 3D NAND flow — one depth, one landing surface — and it is still one of the hardest to etch cleanly, because that landing surface sits at the tightest pitch anywhere in the array.

Channel plug finished
drain-poly etch-back already done
Oxide cap deposited
flat surface over the array top
BLC mask
tight pitch, SADP-defined
BLC etch
single depth, lands on channel plug
Barrier + W fill
contact plug
Bit-line etch (SADP)
M0-level trench, tightest pitch in the array

Every other contact in this flow trades depth control for lateral room; BLC trades the other way.

Bit-Line Contact Etch — Tight Pitch, Landing on Every Channel Plug one contact per channel hole, at the array's tightest pitch, right at the top of the stack bit line (BL) — SADP, very tight pitch channel plugs — drain-poly etch-back finished these earlier 200-300+ layer array stack below — not re-etched here Why pitch dominates bit-line pitch is often the tightest in the whole chip — tighter than word-line pitch often needs self-aligned double patterning (SADP) just to define the BL trench BLC itself must then land on a plug only slightly wider than the contact itself A short, easy-looking etch with almost no margin for error unlike the word-line contact, BLC only has to reach one depth — the top of the channel plug — but the bit-line pitch gives it almost no lateral room: miss the plug sideways and the contact opens onto the surrounding dielectric or an adjacent structure instead of the channel it was meant to reach. next: back-end metal (M1/V1/M2) routes every bit line out to the peripheral sense and decode circuits

BLC lands on the channel plug, and only the channel plug. By the time this etch runs, the drain-poly etch-back from the channel-hole module has already finished shaping the top of every channel hole into a small poly plug, so BLC's entire job is a single, uniform-depth dielectric etch down to that plug — no staircase, no multiple landing depths, no selectivity to different films at different steps.

What makes it hard is how close together those plugs sit. Bit-line pitch is routinely the tightest dimension anywhere on the die, often requiring self-aligned double patterning (SADP) just to define the bit-line trench itself — so a BLC via only slightly wider than its target plug has almost no lateral margin, and a contact that drifts sideways even a little lands on surrounding dielectric or an adjacent structure instead of the channel.

Compare it to word-line contact etch and the trade-off is exact and opposite. WLC has to hit 200 to 300-plus different depths but has comparatively generous lateral spacing between contacts on the staircase; BLC has exactly one depth to hit but almost no lateral room to work with — two contact etches in the same flow, each hard for the opposite reason.

A barrier and tungsten fill finish the contact the same way every other via in the flow does, after which the bit-line metal etch itself — also run at that same tight pitch, often with SADP — routes every one of these contacts out to the peripheral sense amplifiers and decoders that actually read and write the array.

Bit-line contact etch is proof that aspect ratio is not the only thing that makes an etch step critical in 3D NAND: channel hole and TAC are hard because they are deep, but BLC is hard because, at this pitch, there is almost nowhere for the via to go except straight down onto exactly the plug it was meant to find.

Take 3d nand bit line contact etch further

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