3D NAND Slit Bottom Source Line Contact Fill

Slit-bottom source-line contact fill is the step that actually closes the trench the slit module spent several etches preparing, and its hardest problem is not etch chemistry at all — it is getting a tall, narrow opening to fill solid from the bottom up without sealing a void inside it.

Slit walls spacer-lined
floor clear to source plate
Barrier/seed layer
thin, conformal, coats the trench
Bottom-up fill
W or doped poly, no pinch-off
CMP / etch-back overburden
removes fill from the top surface
Source connection complete
slit sealed for good

That risk exists because deposition into a deep trench does not always behave the way it should.

Slit-Bottom Source-Line Contact Fill — Closing a Trench Without a Void a tall, narrow trench has to fill from the bottom up, not pinch shut at the top first array stack — slit walls already spacer-lined, floor already clear barrier/seed layer first (thin, conformal) void-free fill — bottom-up, no pinch-off pinch-off at the top — seals a void inside overburden removed by CMP/etch-back A deposition problem wearing an etch module's name the contact fill step is really about deposition conformality and fill rate, not etch chemistry — but a void left here fails exactly like an etch defect would: an electrical path that looks complete but isn't. the trench this fill enters was shaped by slit etch, opened at the bottom by slit-bottom punch, and lined by slit-spacer etch — three prior etches, one fill

A barrier and seed layer go down first, thin and conformal, coating every exposed surface the slit-spacer etch just finished preparing. This layer exists to give the fill material something to adhere to and nucleate from evenly along the trench, rather than depositing unevenly and favoring one region over another.

The fill itself — tungsten or doped polysilicon — has to grow from the bottom of the trench upward, not close off the top first. A trench this narrow and this deep can pinch shut near its opening before the material below has finished filling in, sealing a void inside the contact that no amount of additional deposition on top can ever reach or repair.

A sealed void produces a contact that looks complete and isn't. Electrically, a void-containing CSL fill can still conduct partially or intermittently, which makes this exactly the kind of defect that often escapes simple continuity checks and only shows up as marginal or unreliable source-line behavior later — the deposition equivalent of an etch that stopped short without anyone noticing at the time.

CMP or an etch-back finishes the job by clearing the overburden. Fill material inevitably coats the top surface of the array during deposition, not just the trench interior, and that excess has to be removed before the slit can be considered sealed and the next module can proceed.

This step inherits every etch that came before it in the slit module. The trench's shape came from the main slit etch, its floor opened from the bottom punch, its walls insulated by the spacer etch — contact fill is the payoff step, and a void here can undo the precision all three of those etches achieved, across Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking alike.

Take 3d nand slit bottom source line contact fill further

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