3D NAND Common Source Line Etch

Common source line, or CSL, etch is the step that finally seals the slit trench for good — after that same opening has already carried the gate-replacement wet etch and the word-line metal fill, it now carries one last contact down to the source-line plate, and this time it has to stay electrically isolated from every word line it passes on the way down.

Replacement gate done
word-line metal fills the cavities
Slit still open
source-line plate exposed below
Slit-spacer etch
insulates sidewalls first
CSL contact fill
W or doped poly, through the slit
Slit sealed
three jobs done through one trench

Getting that isolation right is the entire point of running a spacer etch before the fill, not after it.

Common Source Line (CSL) — the Fill That Closes the Slit a spacer etch, then a contact fill, both run through the same trench the replacement-gate etch just finished using array stack — word lines are now metal, replacement gate done slit-spacer etch (insulates slit sidewalls first) CSL contact fill W or doped poly must not touch adjacent word-line metal slit-bottom punch already opened this plate source-line plate (doped poly or WSi) — CSL lands here Two source-reach paths CSL — vertical, through the slit, from above side-wall ONO removal — lateral, channel reaches source plate from the side both land on the same source-line plate, from two different directions The slit's last job before it is sealed for good once CSL is filled, the slit trench is done: it has carried the gate-replacement wet etch, the metal recess, and now the source-line contact — three different jobs through one physical opening. a spacer failure here shorts the common source to a word line, not to another word line — a different failure signature in test

The slit-spacer etch goes first, and it exists for one reason: without it, the CSL fill would short directly to the word-line metal sitting right next to it in the same trench. An insulating film is etched to leave a thin spacer lining the slit sidewalls, narrowing the open channel down the middle just enough to keep the eventual source contact from touching any of the 200 to 300-plus metal layers it runs past.

CSL fill itself is a straightforward via fill — tungsten or doped polysilicon — but its target is the same source-line plate the slit-bottom punch opened earlier in the flow, during the slit module, before replacement gate ever ran. CSL etch does not create that landing surface; it only has to reach it cleanly, through a trench that has already been used for two other purposes.

CSL and the side-wall ONO removal from the source-formation module are two different paths to the exact same plate. CSL reaches the source-line plate vertically, straight down through the slit from above; side-wall ONO removal reaches it laterally, exposing the channel from the side so it can meet the plate directly — the array's two source connections, built from opposite directions through two different etch families.

A spacer defect here has a distinctive failure signature. Where a bad replacement-gate metal recess shorts one word line to its neighbor, a bad CSL spacer shorts the common source line to a word line instead — a different electrical signature at test, and one that traces straight back to this specific etch rather than to the gate-metal module that ran just before it.

CSL is the quiet last tenant of the slit trench: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all route the source connection back through the same physical opening the replacement-gate etch used, which is why the slit's final state — spacer intact, fill landed cleanly on the source plate — is what actually determines whether the array's source side works at all.

Take 3d nand common source line etch further

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