3D NAND Etch Applications

3D NAND replaces the one flat etch step of a planar chip with close to forty named etch applications, and almost all of them exist to solve one problem: getting a feature straight, or sideways, through 200 to 300-plus alternating layers instead of printing it once on a flat surface. Names differ between Samsung's V-NAND, SK hynix's 4D NAND, Micron's floating-gate and replacement-gate generations, Kioxia/WD's BiCS, and YMTC's Xtacking, but the underlying module list below holds across all of them, built on a CMOS-under-array (CuA/PUC/COP) or a separately bonded CMOS wafer.

The two etches that make 3D NAND possible at all sit at the top and bottom of that loop, and both run at depths a planar chip never has to cross.

• Periphery CMOS, built first. Whether it sits directly under the array (CMOS-under-array, also called PUC or COP) or on a separate wafer that gets bonded on later (YMTC's Xtacking, or a CBA bonded architecture), the periphery etch module looks like ordinary logic: STI trench and recess, a poly/high-voltage gate etch (HV GOX etch) for the dual-oxide high-voltage transistors, gate spacer, peripheral contact (Peri CT), and the under-array M0/V0 metal plus the source-line plate etch that forms the doped-poly or WSi plate the array will later contact from above.

Stack and hard mask set the budget for everything that follows. A thick amorphous-carbon or doped-carbon hard mask (opened, then later stripped by ashing) sits on top of the ONON film stack — alternating SiO2/SiN pairs used by Samsung, SK hynix, Micron, Kioxia/WD and YMTC alike, versus the older SiO2/poly OPOP floating-gate stack some early Micron and Intel designs used — with a DARC/SiON anti-reflective layer opened separately and a stack-edge trim etch defining where the array block ends.

The channel hole is the etch that makes 3D NAND possible at all. Burning through 200 to 300-plus alternating layers at an aspect ratio of 50 to 80-to-1 or more, the channel hole (also called the memory hole, CH, or MH) etch is split into a lower-deck and an upper-deck pass joined by an inter-deck plug or joint etch, because no single etch holds a straight, round profile that deep without bowing, twisting, or CD loading — many fabs now run this step cryogenically just to control the bow. Once both decks are open, a sacrificial-poly recess removes the lower-deck fill, a bottom punch opens the ONO film so the channel reaches the source plate (sometimes after a selective epitaxial recess), and a channel-poly recess, a core-oxide ("macaroni") recess, and a drain-poly etch-back finish the plug at the top.

The memory film and channel liner etches open the transistor itself. An ONO punch (also called blocking/trap/tunnel open) removes the oxide-nitride-oxide charge-trap film at the hole bottom so the channel can contact the source, protected during that punch by a sacrificial-liner strip, while newer nodes add a charge-trap nitride cut (CTN cut) that laterally separates the trap layer between word lines — the etch step behind two-bits-per-hole, split-cell NAND.

Staircase etch spends more process time than almost any other single module, because every one of the 200 to 300-plus word lines needs its own electrical contact landing at a different depth: a photoresist-trim/etch loop (the trim-etch, or "stair etch") repeats dozens of times, often split into multiple zones etched at different depths at once (chop etch, or split-zone staircase) to cut the number of cycles, followed by a step etch that exposes the SiN landing pad on each stair and a staircase-oxide recess after the thick gap-fill oxide and CMP.

Slit, or gate-line-slit (GLS), etch is the long trench that turns a solid stack into separate memory blocks — cut full-depth between blocks, partial-depth inside a block (sub-block slit or cut), and shallower still at the very top and bottom select gates (TSG/SSL cut for the drain select gate, BSG/GSL cut for the source select gate), with a slit-bottom punch opening the source-line plate underneath.

Replacement gate is where gate-all-around 3D NAND actually becomes metal, and it runs entirely through the slit: hot phosphoric acid pulls back (exhumes) every sacrificial SiN layer laterally, an oxide recess smooths the resulting cavities, and a metal etch-back (tungsten, molybdenum on newer nodes, or TiN) recesses the gate metal off the slit sidewalls so word lines don't short to each other — followed by a slit-spacer etch and the common-source-line (CSL) contact fill back through the same trench.

Source formation reaches the channel from below, laterally, through the slit — a sacrificial source-poly strip, a side-wall ONO removal (also called SWC, side-wall-contact etch) that exposes the channel from the side so it can meet the source plate, and a source-poly recess.

Contacts and middle-of-line etching have to hit wildly different depths on one die. Word-line contacts (WLC, staircase contact, or CC) land on every one of the staircase's steps at a different depth and need extreme selectivity to stop cleanly on the step's SiN or tungsten; a through-array contact (TAC/TAV) drops straight through the array to the CMOS below; bit-line contact lands on the channel plug; select-gate and source-line contacts finish the array; and a deep peripheral contact (Peri CT/MC) reaches down to the logic outside the array.

Back end and wafer-bonding etches finish the die the way any advanced logic chip does, plus one extra step for bonded architectures: bit-line trench or via (often cut with self-aligned double patterning at very tight pitch), M1/V1/M2, top aluminum metal, and pad/polyimide opens — and for Xtacking, CBA, or other bonded 4D-NAND-style builds, a hybrid-bonding-pad via, a backside silicon thinning/reveal etch that removes the array wafer's substrate after bonding, a backside source contact, and a through-silicon contact reach back through from the far side of the wafer.

A long tail of supporting etches keeps the other roughly thirty from failing: bevel etch controls edge delamination on stacks this thick and stressed; alignment and overlay keys have to be cut deep enough to survive under the full stack; pre-clean, dry clean, and post-etch polymer-removal steps run after nearly every high-aspect-ratio etch; and dummy channel holes (stress-relief or dummy-hole etch) are cut purely for mechanical support under the staircase.

The next layer-count jump is already changing which of these etches matter most. Cryogenic channel-hole etch, now closer to mainstream than emerging, holds bow and CD loading through 300-plus layers; triple- and quad-deck channel holes multiply the inter-deck plug and alignment etches per hole; a molybdenum metal recess is replacing tungsten in the replacement-gate module to cut resistance; and ferroelectric (FeNAND) film patterning and lateral cell-isolation etches for split-cell designs are the two modules most likely to add new named etch steps next.

Read as a single list, the roughly forty etch applications above are really six repeating problems wearing company-specific names: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron's floating-gate and replacement-gate generations, and YMTC's Xtacking all etch a channel hole straight through 200 to 300-plus layers, cut it open sideways through a slit to swap nitride for metal, land a different-depth contact on every staircase step, and bond or build the periphery CMOS underneath — which is why channel hole, staircase, slit, replacement gate, word-line contact, and, for bonded designs, backside-via etch get singled out as the handful that actually gate yield.