3D NAND Film Stack

The 3D NAND film stack is the foundation every later etch and fill step in the flow depends on: 200 to 300-plus alternating pairs of silicon dioxide and silicon nitride (ONON), deposited one pair at a time by plasma-enhanced CVD, before a single hole is ever etched through it. Get the stack wrong — thickness drifting pair to pair, or stress building up unevenly — and no downstream etch recipe can recover a straight channel hole or a flat wafer.

Wafer prep
periphery CMOS already built
Recipe setup
target pair count, 200-300+
Pair deposition looprepeated 200 to 300+ times
SiO2 deposit
PECVD, 25-35 nm
SiN deposit
PECVD, sacrificial layer
Thickness and stress check
in-line metrology, wafer bow
↻ next pair
Hard mask deposition
thick amorphous/doped carbon
Ready for channel hole etch
lithography next

Two different film-stack philosophies exist in production today, and the choice decides almost everything that happens later in the flow.

The 3D NAND Film Stack — ONON vs. OPOP everything downstream (channel hole, staircase, replacement gate) is cut through this stack ONON — replacement-gate (most vendors) 200-300+ pairs later: SiN is swapped for W/Mo metal each pair ≈ 25-35 nm, PECVD, one pair at a time Samsung V-NAND · SK hynix 4D NAND · Kioxia/WD BiCS · YMTC Xtacking OPOP — floating-gate (legacy) SiO2 / doped poly, charge stored in a conductive floating gate early Micron / Intel 3D NAND Why the stack comes before any etch step film stress and thickness uniformity set the wafer bow budget that the channel-hole and staircase etches must then work within — a stack deposited out of spec cannot be fixed by a better etch recipe downstream. a hard-mask layer (thick amorphous or doped carbon) caps the stack before the first lithography step so the channel hole etch below can hold its mask through the full 200-300+ layer depth

ONON is what Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, and YMTC's Xtacking all deposit, because the nitride in each pair is sacrificial: it gets pulled out later through the gate-line slit and replaced with tungsten or molybdenum metal in the replacement-gate module, which is why the stack has to hold its shape through a chemical removal step it wasn't permanently built with.

OPOP is the older, floating-gate approach some early Micron and Intel 3D NAND designs used, pairing silicon dioxide with doped polysilicon that stores charge directly in a conductive floating gate rather than a charge-trap nitride film — simpler chemistry, but it does not scale to the 200 to 300-plus layer counts that ONON replacement-gate stacks now reach.

Each ONON pair runs roughly 25 to 35 nanometers thick, and because the full stack is deposited before any etch, the cumulative film stress across 200 to 300-plus pairs is what sets the wafer-bow budget every later step — channel hole, staircase, slit — has to work within; a stack that drifts out of its thickness or stress target cannot be corrected by a better etch recipe downstream, only by redepositing it.

A thick hard mask, usually amorphous or doped carbon, caps the finished stack before lithography begins, because that mask is what has to survive the channel-hole etch's full aspect ratio of 50 to 80-to-1 through the entire film stack beneath it — the first etch step in the flow depends entirely on how well this deposition stage finished.

The film stack is the one step in the entire 3D NAND flow with no etch in it at all, and that is exactly why it matters most: every aspect-ratio, bow, and selectivity problem that shows up later in channel hole, staircase, or replacement-gate etch traces back to how evenly this stack was deposited, pair by pair, before any of those steps began.

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