3D NAND Gate Spacer Etch

Gate spacer etch is the step that decides exactly how close a source/drain implant can get to a peripheral transistor's channel, and it does that job the same way slit-spacer etch does on the array side: an anisotropic pass that leaves insulation on the vertical sidewalls while clearing it everywhere flat.

Poly gate etch done
HV and LV gates both cut
Conformal spacer film
coats gate and substrate alike
Anisotropic spacer etch
clears flat surfaces, keeps sidewalls
Extension boundary set
defines where implant can reach
Source/drain implant next
offset from the channel by the spacer

That split outcome is what turns one conformal film into both a protective sidewall and an open implant path at the same time.

Gate Spacer Etch — Setting the Extension Boundary on Every Peripheral Gate an anisotropic etch that leaves insulation on the gate sidewalls, clears everywhere else Silicon substrate — source/drain regions on either side of the gate poly gate conformal liner coats everything first spacer spacer extension implant boundary extension implant boundary Anisotropic for the same reason slit-spacer etch is a spacer left on the flat substrate would block the source/drain implant from reaching its target depth right next to the gate; a spacer removed from the sidewalls too would leave the gate edge unprotected, letting dopant implant too close to the channel and ruining the transistor's threshold behavior. HV and LV gates typically use different spacer widths, because they need different extension offsets for their different operating voltages

A conformal spacer film goes down over the entire gate stack right after poly gate etch finishes, coating the gate top, its vertical sidewalls, and the flat substrate on either side — identically, with no preference yet for where it will ultimately remain.

The anisotropic etch that follows is what creates the asymmetry. Run directionally, it clears the film fastest off horizontal surfaces — the gate top and the substrate — while the vertical sidewalls, hit only glancingly by the same directional etch, keep their spacer intact.

That remaining sidewall spacer sets the extension implant's offset from the channel. The source/drain extension implant that follows this etch can only reach silicon the spacer isn't covering, so the spacer's width directly defines how far from the gate edge the implant lands — too narrow a spacer and the implant encroaches too close to the channel, shortening the effective channel length in a way the design never intended; too wide and the implant lands too far away, adding unwanted series resistance.

HV and LV gates generally need different spacer widths, for the same reason they needed different gate oxide thicknesses. A transistor switching tens of volts needs a wider offset between its channel and its heavily doped source/drain regions to avoid breakdown at the gate edge; a low-voltage logic transistor can run a narrower spacer and recover switching speed instead — meaning this etch's target dimension is not one number but two, depending on which gate it's defining.

Clearing the flat substrate is just as important as keeping the sidewall. If spacer material were left anywhere on the open source/drain area, the extension implant simply couldn't reach the silicon underneath it — the clearing half of this etch is what makes the next step possible at all, not just a cleanup pass.

Gate spacer etch closes out the peripheral transistor module the same way it opens the implant module that follows: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all depend on this single anisotropic etch setting the exact boundary between gate and implant on every HV and LV transistor their periphery needs, before a single dopant atom is driven into the silicon.

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