3D NAND Replacement Gate Etch

Replacement gate is the step where 3D NAND actually becomes a gate-all-around transistor array, and it runs entirely through the slit trench that was just cut: every sacrificial silicon-nitride layer in the ONON stack gets pulled out and swapped for real gate metal, all at once, across 200 to 300-plus layers.

Slit open
full-depth trench reaches every layer
Gate replacement, through the slitruns for every SiN layer at once
SiN pull-back
hot H3PO4, lateral exhume
Oxide recess
smooths the cavity
Metal etch-back
W, Mo, or TiN off sidewalls
↻ no shorts between layers
Slit-spacer etch
insulates the trench
CSL contact fill
common source line
Word-line contacts next
land on staircase, reach new metal

The sequence is chemistry, not photolithography — no new mask is patterned anywhere in this module.

Replacement Gate — Swapping Nitride for Metal, One Slit at a Time every sacrificial SiN layer is pulled out and replaced with W or Mo, reached only through the slit trench Before — ONON, SiN still sacrificial slit After — word lines are now metal slit pull-back + metal fill Four steps, run entirely back through the slit 1. SiN pull-back — hot H3PO4 laterally exhumes every sacrificial nitride layer through the slit 2. Oxide recess — smooths the resulting cavity so the metal fill is uniform 3. Metal etch-back — W, Mo on newer nodes, or TiN, recessed off the slit sidewalls so word lines don't short 4. Slit-spacer etch + CSL fill — insulates the slit, then fills it with the common-source-line contact next: word-line contacts land on the staircase to reach every one of these new metal layers individually

SiN pull-back is a wet etch, not a plasma etch, and it is the step that defines the whole module. Hot phosphoric acid (H3PO4) flows in through the slit and laterally exhumes every nitride layer in the stack, leaving a honeycomb of empty cavities where the sacrificial film used to be — reaching every one of 200 to 300-plus layers from the side, through a trench that may only be a few tens of nanometers wide.

Oxide recess smooths those cavities before any metal goes in, because a rough or uneven cavity wall left over from the wet pull-back becomes a resistance or short-risk hot spot once it is filled with conductive metal.

Metal etch-back is what actually makes a word line, and it has one job: not touching the layer above or below it. Tungsten is the longtime default, molybdenum is increasingly used on newer nodes to cut resistance, and TiN sometimes serves as a barrier layer underneath either one — all deposited to fill the cavity and then recessed back off the slit sidewalls, because any metal left bridging the slit wall would short every word line in the stack together.

Slit-spacer etch and the common-source-line (CSL) contact fill close the trench out. An insulating spacer goes down first so the final tungsten or poly fill that becomes the CSL contact doesn't short to the word-line metal it just replaced, right next door in the same trench.

Replacement gate is why the slit etch mattered in the first place: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all depend on this same wet-pull-back-then-metal-fill sequence to turn a stack of SiO2/SiN pairs into an actual array of gate-all-around transistors, and it is the metal etch-back's recess depth — not the channel hole, not the staircase — that most directly decides whether two adjacent word lines short or stay isolated.

Take 3d nand replacement gate etch further

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