3D NAND Through Array Contact Etch
Through-array contact etch, TAC or TAV, is the one etch in the entire 3D NAND flow that deliberately avoids every structure the rest of the process just spent dozens of modules building — it drops straight down through a clean oxide path to reach the periphery CMOS underneath, skipping the word lines, channel holes, and slit entirely.
That straight shot only works because a region of the array is left empty on purpose, specifically to carry this contact.
TAC exists because the periphery sits underneath the array, not beside it. In a CMOS-under-array design (CuA/PUC/COP), the only electrical path from a signal routed above the array down to the logic transistors below it is straight through the memory stack — and TAC is that path, cut through a dummy oxide region set aside with no word lines, no channel holes, and no slit anywhere near it.
The etch itself is comparatively simple chemistry, because there is nothing selective to stop on halfway down. Unlike a word-line contact, which has to land precisely on one of 200 to 300-plus different depths, TAC is a single high-aspect-ratio etch through a uniform oxide fill from the top of the stack to a periphery metal landing pad or via at the bottom — no replacement-gate metal, no staircase steps, no charge-trap film to avoid.
The dummy region is the real cost of this contact, not the etch. Every square of array area given over to a TAC's dummy oxide zone is area that cannot hold channel holes or word lines, so designers place as few TAC vias as the periphery signal count allows, trading array density directly for however many through-array paths the design needs.
Bonded architectures don't need this etch at all. YMTC's Xtacking and other CBA-style designs build the periphery CMOS on a separate wafer and join it to the array wafer with hybrid-bonding pads and vias instead, which is why TAC specifically shows up in CuA/PUC designs from Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, and Micron, and is largely absent from bonded flows.
TAC is the deliberate exception to every other etch in this flow: where channel hole, staircase, slit, and word-line contact etch all exist to interact precisely with the array's own layered structure, through-array contact exists only to get around it — the fastest path down is the one that touches nothing on the way.