3D NAND Through Silicon Contact Etch

Through-silicon contact, or TSC, is an etch that simply does not exist in a CMOS-under-array chip, because it only becomes necessary once a design has already bonded two separate wafers together and then ground away the array wafer's own substrate to get at it from behind.

Array and periphery wafers bonded
hybrid-bond pads joined
Backside Si thinning / reveal
removes array wafer's own substrate
TSC mask, new backside
deep via pattern from the far side
TSC etch
reaches into the array from behind
Contact fill
barrier + W plug
Backside routing
signals reach the array from behind

That sequence — bond first, thin second, etch third — is what makes TSC the signature access route of bonded 3D NAND architectures rather than a universal step.

Through-Silicon Contact — Reaching In From the Back of a Bonded Wafer the etch that only exists after the array wafer's own silicon has been thinned away Periphery CMOS wafer (built separately) joined by hybrid-bond vias below hybrid-bond pads array stack, now flipped — backside faces up after thinning bulk substrate removed by backside Si thinning/reveal etch TSC etch from the new backside, down into the array Why this etch has no counterpart in a CuA design a CMOS-under-array chip never flips a wafer and never removes its own substrate, so it reaches the periphery with TAC, straight through the array from the original top. A bonded design has already joined its periphery wafer underneath and thinned the array's own substrate away — TSC is the etch that reaches back in from that new backside surface, a route that simply does not exist in CuA. YMTC's Xtacking and other CBA-style bonded designs use TSC in place of TAC — same goal, opposite wafer, opposite direction

Bonded architectures build the periphery on its own wafer and join it to the array afterward. In YMTC's Xtacking and other CBA-style (bonded) designs, the periphery CMOS is fabricated separately, flipped, and joined to the array wafer through hybrid-bonding pads — a fundamentally different starting point from a CMOS-under-array chip, where the periphery and array share one continuous wafer from the start.

Backside silicon thinning removes the one thing standing in the way: the array wafer's own bulk substrate. Once the two wafers are bonded, the array wafer's original backside silicon serves no further purpose and is ground and etched away, exposing a brand-new backside surface that the original CMOS-under-array design never has to create or use.

TSC etches down from that new backside surface, into the array, to make an electrical connection the hybrid-bond pads alone don't provide everywhere they're needed. It is, functionally, this architecture's answer to the same problem TAC solves in a CuA design — a path that skips the array's own memory structures to reach a circuit elsewhere — but reached from the opposite direction, because the wafer itself has been flipped and thinned to make that direction available.

A barrier and tungsten plug finish the contact the same way most vias in this flow do, after which backside routing carries signals into the array from behind — a wiring layer that a CuA design, with its original substrate still intact and never exposed from that side, has no equivalent for.

TSC is proof that "through-array contact" and "through-silicon contact" solve the same category of problem — reaching a destination without using the array's own memory path — from genuinely different starting conditions: TAC works because the array's original top surface is still accessible in a CuA stack; TSC works because the array's original bottom surface has been removed and replaced with a new backside in a bonded one.

Take 3d nand through silicon contact etch further

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