3D NAND Word Line Contact Etch

Word-line contact etch is the step that finally reaches every one of the 200 to 300-plus word lines the replacement-gate module just finished building, and it has to do it from one flat exposure that lands at a different depth on every single landing pad the staircase etch carved out.

Replacement gate done
word lines are now metal
Oxide gap-fill + CMP
flat top surface over staircase
Contact mask, one exposure
resist thickness tuned per depth
WLC dielectric etchall 200-300+ contacts etched together
Timed bulk etch
removes most of the oxide depth
Selective landing etch
stops on step SiN or metal
Contact fill
W plug, barrier/liner first
Back end next
BL/M1/M2 route each contact out

That one-mask, many-depths problem is the entire reason this step is treated as its own etch module rather than an ordinary contact etch.

Word-Line Contact Etch — One Mask, a Different Depth on Every Step every contact is etched from the same top surface but must stop at a different landing depth single contact mask, uniform resist thickness across all depths Why this is hard shallow contacts: risk punching through into the layer below deep contacts: risk not reaching the landing pad at all needs selectivity to step SiN or W, not just a timed etch one contact per word line, 200-300+ total WLC, staircase contact, or CC — same job, three names one dielectric etch, one mask, but 200 to 300+ different stopping depths in the same exposure — solved by tuning photoresist thickness per-contact and etch selectivity to the step's SiN or metal, not by running the etch for different lengths of time on different contacts. neighbors: TAC drops straight to the CMOS below; BLC lands on the channel plug; Peri CT reaches the logic outside the array

The names differ by vendor, but the job is identical. WLC, staircase contact, and CC (contact to control gate) all describe the same dielectric etch landing on the SiN or metal pad exposed by the staircase-oxide recess — Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking each call it something slightly different while running essentially the same step.

Depth is controlled before the etch even starts, not during it. Because every contact sits above a different step and therefore a different oxide thickness, the photoresist above each one is tuned to a different thickness during the single contact-mask exposure, so a uniform timed etch still reaches a usable depth at each contact rather than finishing shallow contacts too early or deep ones too late.

Extreme etch selectivity is what prevents the two failure modes that threaten every contact at once. A contact landing on a shallow step risks punching straight through its thin landing pad into the word line below it, shorting two layers together; a contact landing on a deep step risks stopping short of its pad entirely, leaving an open circuit — so the etch chemistry has to stop cleanly on the exposed SiN or tungsten regardless of how much oxide sits above it.

Once the dielectric etch lands, a barrier/liner and a tungsten plug fill every contact before the back-end module routes each one out individually through bit-line and metal layers — which is also why a single bad word-line contact shows up as one dead layer in test, not a dead die, unlike a channel-hole or slit defect that can take out an entire column or block.

Word-line contact etch is where the staircase etch's entire purpose gets collected: every trim-etch cycle that module ran, one per landing depth, exists only so this step can reach each of 200 to 300-plus metal layers from the same flat surface without ever re-masking the wafer between contacts.

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